INSTRUCTION SET REFERENCE

Table A-9. Instruction Execution Times (in State Times) (Continued)

Arithmetic (Group II)

 

 

 

 

Indirect

 

 

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mnemonic

Direct

Immed.

Normal

 

 

Autoinc.

Short

 

Long

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg.

Mem.

Reg.

Mem.

Reg.

Mem.

Reg.

Mem.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIV

26

27

28

31

 

 

29

32

29

32

30

 

33

DIVB

18

18

20

23

 

 

21

24

21

24

22

 

25

DIVU

24

25

26

29

 

 

27

30

27

30

28

 

31

DIVUB

16

16

18

21

 

 

19

22

19

22

20

 

23

MUL (2 ops)

16

17

18

21

 

 

19

22

19

22

20

 

23

MUL (3 ops)

16

17

18

21

 

 

19

22

19

22

20

 

23

MULB (2 ops)

12

12

14

17

 

 

15

18

15

18

16

 

19

MULB (3 ops)

12

12

14

17

 

 

15

18

15

18

16

 

19

MULU (2 ops)

14

15

16

19

 

 

17

19

17

20

18

 

21

MULU (3 ops)

14

15

16

19

 

 

17

19

17

20

18

 

21

MULUB (2 ops)

10

10

12

15

 

 

13

15

12

16

14

 

17

MULUB (3 ops)

10

10

12

15

 

 

13

15

12

16

14

 

17

 

 

 

Logical

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Indirect

 

 

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mnemonic

Direct

Immed.

Normal

 

 

Autoinc.

Short

 

Long

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg.

Mem.

Reg.

Mem.

Reg.

Mem.

Reg.

Mem.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AND (2 ops)

4

5

6

8

 

 

7

9

6

8

7

 

9

AND (3 ops)

5

6

7

10

 

 

8

11

7

10

8

 

11

ANDB (2 ops)

4

4

6

8

 

 

7

9

6

8

7

 

9

ANDB (3 ops)

5

5

7

10

 

 

8

11

7

10

8

 

11

NEG

3

 

 

NEGB

3

 

 

NOT

3

 

 

NOTB

3

 

 

OR

4

5

6

8

 

 

7

9

6

8

7

 

9

ORB

4

4

6

8

 

 

7

9

6

8

7

 

9

XOR

4

5

6

8

 

 

7

9

6

8

7

 

9

XORB

4

4

6

8

 

 

7

9

6

8

7

 

9

NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to all memory-mapped registers, I/O, or memory. See Table 4-1 on page 4-2 for address information.

A-53

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Image 442
Intel 8XC196MH, 8XC196MD, 8XC196MC Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem, DIV Divb Divu Divub, Logical