Index | Intel 8XC196MC, 8XC196MD, 8XC196MH instruction

#, defined, 1-3, A-1 16-bit data bus

read cycles, 15-14 timing diagram, 15-15 write cycles, 15-14

8-bit data bus

read cycles, 15-16 timing diagram, 15-17 write cycles, 15-16

A

A/D command register, 12-8, C-6 A/D converter, 2-11, 12-1–12-18

actual characteristic, 12-16 and port 0 reads, 12-13 and PTS, 5-32–5-37 block diagram, 12-1 calculating result, 12-9, 12-13 calculating series resistance, 12-10 characteristics, 12-15–12-18 conversion time, 12-6 determining status, 12-9

errors, 12-13–12-18

hardware considerations, 12-10–12-13 ideal characteristic, 12-15, 12-16 input circuit, suggested, 12-12

input protection devices, 12-12 interfacing with, 12-10– 12-13 interpreting results, 12-9 interrupt, 12-8

minimizing input source resistance, 12-11 overview, 12-3–12-4

programming, 12-4–12-8 sample delay, 12-4 sample time, 12-6 sample window, 12-4 SFRs, 12-2

signals, 12-2

starting with PTS, 5-32–5-37 successive approximation

algorithm, 12-4 register (SAR), 12-4

terminal-based characteristic, 12-18 threshold-detection modes, 12-5

INDEX

transfer function, 12-15–12-18 zero-offset adjustment, 12-3, 12-5 zero-offset error, 12-16

See also port 0

A/D result register (read), 12-9, C-7 A/D result register (write), 12-6, C-8 A/D scan mode‚ See PTS

A/D test register, 12-5, C-9 A/D time register, 12-7, C-10 AC timing

specifications, 15-31–15-34 symbol explanations, 15-33

Accumulator, RALU, 2-5 ACH13:0, B-13 AD_COMMAND, C-68 AD_RESULT, 12-9, C-68 AD_TEST, C-68 AD_TIME, C-68 AD15:0, B-13

ADD instruction, A-2, A-7, A-41, A-42, A-47, A-52

ADDB instruction, A-2, A-7, A-42, A-43, A-47, A-52

ADDC instruction, A-2, A-7, A-44, A-47, A-52 ADDCB instruction, A-2, A-8, A-44, A-47, A-52 Address space

map, 4-2

See also memory partitions Address valid strobe mode

ALE/ADV# comparison, 15-27 example system, 15-28, 15-29 signals, 15-27

Address valid with write strobe mode example system, 15-31 signals, 15-30

Address/data bus, 2-6 multiplexing, 15-10–15-17

Addressing modes, 3-5–3-6, A-6 ADV#, B-13

AINC#, 16-12, B-14 ALE, B-14

idle, powerdown, reset status, B-23, B-25 Analog outputs, generating, 10-10 Analog-to-digital converter‚ See A/D converter

Index-1

Image 566

Intel 8XC196MC, 8XC196MD, 8XC196MH manual Index

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual Application Example PWM Signals and RegistersFunctional Overview Programming the Frequency Generator Programming the Waveform Generator Chapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Manual Contents Chapter Guide to this Manual Special Operating Modes Notational Conventions and Terminology Assert and deassert Numbers Related Documents Title Order Number Handbooks and Product InformationApplication Notes, Application Briefs, and Article Reprints MCS 96 Microcontroller Datasheets Commercial/Express MCS 96 Microcontroller Datasheets Automotive This Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank Product Literature World Wide WebTechnical Support Page Architectural Overview Page Microcontroller Features Typical Applications Otprom Features of the 8XC196Mx Product FamilyFunctional Overview SIO PWM CPU ROMPTS EPA PWM WDT SIO RAM Register Arithmetic-logic Unit Ralu CPU ControlRegister File Code Execution Instruction Format Interrupt Service Memory Interface Unit Internal Timing Clock Circuitry Internal Peripherals State Times at Various Frequencies 1 I/O Ports Serial I/O SIO Port Frequency Generator Event Processor Array EPA and Timer/CountersPulse-width Modulator PWM Waveform Generator Testing the Printed Circuit Board Watchdog TimerReducing Power Consumption Analog-to-digital Converter Programming the Nonvolatile Memory Programming Considerations Page Operand Type No. Signed Possible Values Addressing Overview of the Instruction SETOperand Type Definitions Restrictions SHORT-INTEGER Operands BIT OperandsByte Operands Word Operands Integer Operands DOUBLE-WORD Operands Conditional Jumps LONG-INTEGER OperandsConverting Operands Floating Point Operations Addressing Modes Indirect Addressing Direct AddressingImmediate Addressing Definition of Temporary Registers Indirect Addressing with the Stack Pointer Indexed AddressingIndirect Addressing with Autoincrement Short-indexed Addressing Long-indexed Addressing Zero-indexed Addressing Software Standards and Conventions Assembly Language Addressing Mode SelectionsUsing Registers Addressing 32-bit Operands Linking Subroutines Software Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page Program and Special-purpose Memory Memory PartitionsExternal Devices Memory or I/O Device Program MemoryMemory Map Description Addressing Modes Reserved Memory Locations Special-purpose MemorySpecial-purpose Memory Addresses Interrupt and PTS Vectors Security Key Chip Configuration Bytes CCBsSpecial-function Registers SFRs Memory-mapped SFRs Peripheral SFRs Port 2 SFRs EPA and Timer SFRsPeripheral SFRs 8XC196MC SFRs Peripheral SFRs 8XC196MD Ports 2 and 7 SFRs Port 1 SFRs Peripheral SFRs 8XC196MHPort 0 and 2 SFRs Serial I/O Port SFRs Register File Memory Map Address Stack Pointer SP Register File Memory AddressesGeneral-purpose Register RAM Device and Hex Address Range Description Addressing Modes Address High Odd Byte Low Even Byte CPU Special-function Registers SFRsCPU SFRs 02FFH 01FFH Windowing8XC196MC,MD 00FFH Bit Function Number Selecting a WindowWSR WSR Value for Peripherals Addressing a Location Through a Window 10. Selecting a Window of the Upper Register File Base WSR Value WSR Value for 11. Windows12. Windowed Base Addresses Peripheral SFRs 2.3 128-byte Windowing Example 2.1 32-byte Windowing Example2.2 64-byte Windowing Example Unsupported Locations Windowing Example Using the Linker Locator to Set Up a Window ?WSR This listing shows the disassembled code Windowing and Addressing Modes LDB WSR, #12HPage Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Overview of Interrupts Flow Diagram for PTS and Standard Interrupts Interrupt and PTS Control and Status Registers Interrupt Signals and RegistersInterrupt Signals Ptssel Interrupt Sources and PrioritiesPipend 1FBEH Ptssrv Interrupt Source Mnemonic Name Vector Priority Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Unimplemented Opcode Special InterruptsExternal Interrupt Pin Software Trap Multiplexed Interrupt Sources Waveform Generator Protection Circuitry Flow Diagram for the Ovrtm Interrupt Situations that Increase Interrupt Latency End-of-PTS InterruptsInterrupt Latency Calculating Latency Standard Interrupt Latency Standard Interrupt Response Time PTS Interrupt Latency Execution Times for PTS Cycles PTS Mode Execution Time in State TimesProgramming the Interrupts Standard and PTS Interrupts 8XC196MD Ptssel8XC196MC Bit Function Bit Mnemonic Interrupt Standard Vector IntmaskCOMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 Ovrtm COMP2 MC, MD NMI Extint EPA5 INTMASK1NMI Extint NMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 Bit Function Number Mnemonic Pimask8XC196MC 8XC196MD OVRTM1 Modifying Interrupt PrioritiesPimask Standard and PTS Interrupts Determining the Source of an Interrupt 10. Interrupt Pending Intpend Register Intpend 11. Interrupt Pending 1 INTPEND1 Register INTPEND1 12. Peripheral Interrupt Pending Pipend Register Pipend Initializing the PTS Control Blocks Pipend Specifying the PTS Count 14. PTS Service Ptssrv Register Ptssrv Ptscon Selecting the PTS ModeSingle Transfer Mode Register Location Function PTS Single Transfer Mode Control BlockPtsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon Ptscount Ptsdst Ptscb + Standard and PTS Interrupts Block Transfer Mode Ptscb Block Transfer ModeSingle Transfer Mode Ptscb PTS Block Transfer Mode Control Block Ptsblock Ptscb + 5 A/D Scan Mode PTS A/D Scan Mode Control Block A/D Scan Mode Command/Data Table Address Contents 5.1 A/D Scan Mode Cycles 5.2 A/D Scan Mode Example PTSPTR2 H = 1FH PTSPTR2 L = AAH Command/Data Table ExampleA/D Scan Mode Ptscb Example Ptscount = 04H 11. A/D Scan Mode Ptscb Example 5.3 A/D Scan Mode Example10. Command/Data Table Example Serial I/O Modes Ptsvec PTS Serial I/O Mode Control Block 1 8XC196MC, MDSA1 SA0 MAJ SA1 BaudEpareg SA0 † 8XC196MC, MD, MH USER’S Manual Port Address Pointer high byte PTS Serial I/O Mode Control Block 2 8XC196MC, MDPort Mask Register Rpar DataPTSCON1 Portreg PTS Serial I/O Mode Control Block8XC196MC, MD Register Location Function 8XC196MC, MD, MH USER’S Manual 13. Ssio Transmit Mode PTSCBs PTSCB1 PTSCB2 Txddone = Synchronous SIO Receive Mode Example 23. Synchronous SIO Receive Timing 14. Ssio Receive Mode PTSCBs Clrb Rxddone Standard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS Asynchronous SIO Receive Mode Example 27. Asynchronous SIO Receive Timing Portreg H = 1FH P2PIN 16. Asio Receive Mode PTSCBsSamptime = 01H Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page Port Bits Type Direction Associated Peripherals I/O Ports OverviewDevice I/O Ports Standard Input-only Port Pins INPUT-ONLY Ports 1 MC, MD only 1FDAH MH Standard Input-only Port OperationInput-only Port Registers P1PIN MC, MD Standard Input-only Port Considerations Bidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Bidirectional Port Pins Port Pin Special-function Associated Signals Bidirectional Port Operation Bidirectional Port Control and Status Registers Ports Bidirectional Port Structure Sfdir Bidirectional Port Pin ConfigurationsLogic Table for Bidirectional Ports in I/O Mode 8XC196MC, MD, MH USER’S Manual Port Configuration Example Bidirectional Port Pin Configuration ExampleControl Register Values for Each Configuration Bidirectional Port Considerations HZ1 P5.1/INST Bidirectional Ports 3 and 4 ADDRESS/DATA BUS Ports 3 and 4 PinsPort Pins Special-function 12. Ports 3 and 4 Control and Status Registers Bidirectional Ports 3 and 4 Address/Data Bus Operation Address/Data Bus Ports 3 and 4 Structure Standard OUTPUT-ONLY Port Using Ports 3 and 4 as I/ODesign Considerations for Ports 3 13. Logic Table for Ports 3 and 4 as Open-drain I/O Output-only Port Operation Configuring Output-only Port Pins14. Standard Output-only Port Pins 15. Output-only Port Control Register 1FC0H Reset State 0000HWgoutput Port Address OP1 OP0 Reset State 0000H Wgoutput PortPage Serial I/O SIO Port Page SIO Block Diagram Serial I/O SIO Port Functional Overview Serial Port Control and Status Registers Serial I/O Port Signals and RegistersSerial Port Signals P1REG 1F9DH P1DIR 1F9BHP1PIN 1F9FH Serial Port Modes Synchronous Modes Modes 0 Mode Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Mode 2 and 3 Timings Multiprocessor Communications Programming the Control Register Configuring the Serial Port PinsProgramming the Serial Port SP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Bit Function BV7 Programming the Baud Rate and Clock SourceClksrc BV9 BV8 Baudvalue = Bclk 80CFH SPxBAUD Values When Using XTAL1 at 16 MHzEnabling the Serial Port Interrupts E82BH RPE/RB8 Determining Serial Port StatusRPE/RB8 TXE 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Port Frequency Frequency Generator SignalFrequency Generator Control and Status Registers Programming the Frequency Configuring the OutputProgramming the Frequency Generator Freqgen Freqcnt Determining the Current Value of the Down-counterApplication Example Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Chapter Waveform Generator Waveform Generator Functional Overview Waveform Generator Block Diagram Waveform Generator Control and Status Registers Waveform Generator Signals and RegistersWaveform Generator Signals Waveform Generator Operation Timebase Generator Phase Driver Channels Control and Protection Circuitry Register Buffering and Synchronization Protection Circuitry Operating Modes Operation in Center-aligned and Edge-aligned Modes Register UpdatesEvent Mode Step Center-aligned Modes Edge-aligned Modes Center-aligned Modes Center-aligned Modes Counter Operation Center-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Programming the Waveform Generator Configuring the OutputsOutput Configuration PE6 Wgoutput Waveform GeneratorOP1 OP0 Sync PE7 OP1 8XC196MC, MD, MH USER’S Manual E0H WgprotectF0H 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic Reload Specifying the Carrier Period and Duty CycleWgreload 150 Reload Wgcomp Address 1FC2H,1FC4H,1FC6H Wgcounter = Wgreload WgcontrolDT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0 Wgcounter Determining the Waveform GENERATOR’S StatusEnabling the Waveform Generator Interrupts Xxxxh Wgcount WGCOUNT= Design ConsiderationsDead Time and Duty Cycle Wgcomp Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page Chapter PULSE-WIDTH Modulator PWM Functional Overview PWM Signals and Registers PWM Signals PEx Pin Output PWM OperationPWM Control and Status Registers FFH Programming the Frequency and PeriodE6H PWM Output Frequencies Fpwm Pwmperiod Programming the Duty Cycle Pwmperiod + PWM xCONTROL Address 10-3 Sample CalculationsReading the Current Value of the Down-counter PWM Output Alternate Functions PWM Output Alternate Port Function PWM Output Enabled WhenEnabling the PWM Outputs Pwmcount Waveform Generator Output Configuration Wgoutput Register D/A Buffer Block Diagram Generating Analog Outputs Event Processor Array EPA Page Device Capture/Compare Channels Compare-only Channels EPA Functional OverviewEPA Channels COMP30 EPA and TIMER/COUNTER Signals and Registers EPA and Timer/Counter Signals EPA Control and Status Registers P0PIN 1FA8H P1PIN 1FA9H TIMER2 1F7EH TIMER/COUNTER Functional OverviewTIMER1 1F7AH T1RELOAD EPA Timer/Counters Cascade Mode Timer 2 Only Quadrature Clocking Modes State of Xinternal State of Yinternal Count Direction T1DIR Quadrature Mode Timing and Count EPA Channel Functional Overview Operating in Capture Mode A Single EPA Capture/Compare Channel EPA Simplified Input-capture Structure EPA Overruns Action Taken When a Valid Edge OccursOverwrite Bit Status Action Taken When a Valid Edge Occurs EPAxCON.0 Generating a Low-speed PWM Output Operating in Compare ModePreventing EPA Overruns Generating the Highest-speed PWM Output Programming the Timers Programming the EPA and TIMER/COUNTERSConfiguring the EPA and Timer/Counter Signals Clock Source Direction Source Prescaler Divisor Resolution †T1CONTROL Prescaler Resolution † T2CONTROL Programming the Capture/Compare Channels Example EPA Control Register Settings for Channels 1, 3, orMode WGR ROT ON/RT EPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Capture Mode EventCompare Mode Action = 0, 2 = 1, 3 For EPA capture/compare channels 0, 2 EPA xCON Address= 0, 2 For EPA capture/compare channels 1, 3 Capture Mode on Compare Mode RT Comp xCON Address = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00HProgramming the Compare-only Channels WGR ROT Enabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 12.1 A/D Converter Functional Overview Angnd Port Pin Signal Description 12.2 A/D Converter Signals and RegistersA/D Converter Pins A/D Control and Status Registers 12.3 A/D Converter Operation P1PIN MC,MD Programming the A/D Converter OFF1 OFF0 Programming the A/D Test RegisterAdtest Programming the A/D Time Register Adresult Write Programming the A/D Command Register Adtime Enabling the A/D Interrupt AdcommandM1 M0 Mode ACH3 ACH2 ACH1 ACH0 ADRLT90 Determining A/D Status and Conversion ResultsAdresult Read Designing External Interface Circuitry Idealized A/D Sampling Circuitry Minimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Understanding A/D Conversion Errors Using Mixed Analog and Digital Inputs 12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page Minimum Connections Minimum Required SignalsRESET# Unused Inputs I/O Port Configuration GuidePort Where to Find Configuration Information 13.1.2 I/O Port Pin Connections Minimum Hardware Connections Applying and Removing Power Noise Protection Tips ON-CHIP Oscillator Circuitry On-chip Oscillator Circuit External Crystal Connections Using AN External Clock Source External Clock Connections Resetting the Device Reset Timing Sequence Rsts GenconRsts DR0 DRO Generating an External Reset Internal Reset Circuitry 10. Minimum Reset Circuit Issuing an Illegal Idlpd Key Operand Issuing the Reset RST InstructionEnabling the Watchdog Timer Generating Wait States 1EH E1H Selecting the Watchdog Reset Interval 8XC196MH onlyFirst Byte Second Byte Reset Interval 1EH A1HPage Special Operating Modes Page Port Pin Signal Type Description Special Operating Mode Signals and RegistersOperating Mode Control Signals Clkout ONCE# Operating Mode Control and Status RegistersPort Pin Signal Type Description Name CCR0 P7MODEMD 1FD1H Reducing Power ConsumptionP1MODEMH P1REG MH 1F9DH Idle Mode Clock Control During Power-saving Modes Powerdown Mode Enabling and Disabling Powerdown Mode Generating a Hardware Reset Entering Powerdown ModeExiting Powerdown Mode Driving the VPP Pin Low Asserting the External Interrupt Signal External RC Circuit Selecting R1 and C1 Typical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page Signal Port Pin Type Description Name External Memory Interface Signals and RegistersExternal Memory Interface Signals ADV# CCR0.1 Bytes AccessedBHE# AD0 CCR1.2 Buswidth WR# Signal Port PinEA# WRL# External Memory Interface RegistersWRH# Register Address Description Mnemonic BHE#/WRH# † Chip Configuration Registers and Chip Configuration BytesP5REG = 11XX Xxxxb 15-6 LOC1 LOC0 CCR0LOC1 LOC0 IRC1 IRC0 ALE BW0 IRC2 IRC1 IRC0 BW1 BW0 CCR0ALE WDE CCR1WDE BW1 IRC2 BUS Width and Multiplexing CCR1 Multiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Timing Requirements for Buswidth Buswidth Signal Timing DefinitionsSymbol Definition 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Wait States Ready Control Timings for 8-bit Buses 15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup Bus-control Modes Bus-control Mode Bus-control Signals CCR0.3 CCR0.2BUS-CONTROL Modes Standard Bus-control Mode BHE# WR# AD0 CS# ALE OE# WE# RD# WR# OE# WE# RD# WR# Buswidth CS#Eprom RAM Write Strobe Mode 14. Write Strobe Mode 15 -bit System with Writes to Byte-wide RAMs OE# OE# WE# RD# WRH# WRL# Address Valid Strobe Mode 16. Address Valid Strobe Mode 18 -bit System with Flash Eprom OE# RD# Address Valid with Write Strobe Mode 20. Timings of Address Valid with Write Strobe Mode WRH# WRL# CS# System BUS AC Timing SpecificationsVCC Buswidth WE# CS# 22. System Bus Timing External Memory Systems Must Meet These Specifications Explanation of AC SymbolsAC Timing Symbol Definitions Signals AC Timing Definitions Microcontroller Meets These Specifications Address Setup to ALE/ADV# Low 15-35 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Programming Methods Otprom Memory MAP C196Mx Otprom Memory Map Security FeaturesControlling Access to Internal Memory Address Range Description Hex Controlling Access to the Otprom During Programming Modes Controlling Access to the Otprom During Normal OperationMemory Protection for Normal Operating Mode Read Protect Write Protect Protection Status Pccb CCB Memory Protection Options for Programming ModesSecurity Key Controlling Fetches from External Memory To set this bit Write this value To this location Uprom Programming Values and Locations for Slave ModeUsfr PPW Programming Pulse WidthPpwvalue BitBitFunction Number Mnemonic 8XC196MC, MD 8XC196MH Two 250-µs pulses required Modified QUICK-PULSE AlgorithmExample Ppwvalue Calculations Ppwvalue = Modified Quick-pulse Algorithm Programming Mode Pins Special Program Port Pin Cpver PROG#AINC# PACT# Pmode Values Selecting the Programming ModeEntering Programming Modes Power-down Sequence Power-up and Power-down SequencesPower-up Sequence Slave Programming Mode Reading the Signature Word and Programming Voltages Device Signature Word Programming VCC Slave Programming Circuit and Memory MapDevice Signature Word and Programming Voltages Location Value Description Address Comments Slave Programming Mode Memory MapOperating Environment Bit Mnemonic Function CCR1, CCR0LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2 Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine MnemonicDescription Timing Mnemonics10. Timing Mnemonics Mnemonic Description Auto Programming ModeAuto Programming Circuit and Memory Map 12. Auto Programming Circuit Auto Programming Routine Address Internal Address Using Output fromAddress Internal Address Using 11 XC196MC/MD Auto Programming Memory Map 13. Auto Programming Routine Auto Programming Procedure ROM-dump Mode Pccb and Uprom Programming 8XC196MH only 14. Pccb and Uprom Programming Circuit 13. Pccb and Uprom Programming Values Pins Pccb Programming Uprom ProgrammingRUN-TIME Programming PMODE30 0DH 15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Opcode Map Left Half Opcode Table A-1. Opcode Map Right Half Instruction Quotient Stored Flag Set if Quotient is Table A-2. Processor Status Word PSW FlagsValue of Bits Shifted Off Instruction Jumps to Destination if Continues if Table A-4. PSW Flag Setting SymbolsSymbol Description Table A-5. Operand Variables Variable Description Mnemonic Operation PSW Flag SettingsTable A-6. Instruction Set C V VT ST Andb Instruction FormatDest ← Dest and SRC PTRS, Cntreg Count Count ← Count Count ← Cntreg Loop Srcptr ← Ptrs DstptrDstptr ← Srcptr Ptrs ← Srcptr + Dest Clear BYTE. Clears the value Mnemonic Operation Instruction Format ← Dest MOD SRC Dest MOD SRC Djnz Decrement and Jump if not Zero Djnzw Decrement and Jump if not Zero Epts Dpts Disable Peripheral TransactionEpts Enable Peripheral Transaction EXT SIGN-EXTEND Integer Into Long Extb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign MUL Mulb Mulu Mulub Integer operand SRC, Dest Dest ← not Dest Dest ← Dest or SRC INTMASK1/WSR ← SP PSW/INTMASK ← SP SP ← PSW/INTMASK PSW/INTMASK ← SP ← INTMASK1/WSR INTMASK1 ← Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Shrl Logical Right Shift DOUBLE-WORD Skip Rightmost operand SUB Subc SubbSubc Subtract Words with Borrow DEST, SRC Subcb Subtract Bytes with Borrow DEST, SRC Tijmp TBASE, INDEX, #MASK Index and #MASK = Offset× Offset + Tbase = Dest XOR Dest ← Dest XOR SRC Clrb Notb Negb Table A-7. Instruction OpcodesHex Code Instruction Mnemonic Decb Extb Incb Shrb Shlb Shrab Hex Code Hex Code 8XC196MC, MD, MH USER’S Manual Dpts Epts EF Lcall DIV/DIVB/MUL/MULB Note Subc Subcb Table A-8. Instruction Lengths and Hexadecimal OpcodesArithmetic Group Direct Immediate Indirect Indexed Mnemonic Logical Direct Immediate Indirect Data Direct Stack Direct Immediate Indirect Indexed MnemonicOpcode Length Jump Direct Conditional Jump Direct Immediate Call Direct Immediate Indirect Indexed MnemonicLength Opcode PTS Shift Mnemonic Direct Immediate Indirect IndexedSpecial Mnemonic Direct Immediate Indirect Mnemonic Direct Immediate Indirect Normal Autoinc Short Long Reg Mem Table A-9. Instruction Execution Times in State TimesArithmetic Group Indirect Mem Reg Logical Mnemonic Direct Immed Normal Autoinc Short Long Reg MemDIV Divb Divu Divub Reg Mem Stack Register IndirectNormal Autoinc Short Autoinc Short Long Autoinc Short Long RegLDB Ldbse Ldbze STB XCH Xchb Ljmp Sjmp Tijmp Conditional Jump Mnemonic Call Memory Indirect Indexed Mnemonic DirectNormal Autoinc Short Long Clrc Clrvt Idlpd Shift Mnemonic DirectIndirect Indexed NOP RST Setc SkipPage Signal Descriptions Page Table B-1. Signal Name Changes Signal Name ChangesFunctional Groupings of Signals New Name Table B-2 XC196MC Signals Arranged by Functional Categories Figure B-1 XC196MC 64-lead Shrink DIP Sdip Package U8XC196MC Figure B-2 XC196MC 84-lead Plcc Package X8XC196MC Figure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package Table B-3 XC196MD Signals Arranged by Functional Categories P7.7/FREQOUT Figure B-4 XC196MD 84-lead Plcc Package X8XC196MD Figure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package P2.7/SCLK1#/BCLK1 Table B-4 XC196MH Signals Arranged by Functional CategoriesEA# Extint NMI ONCE# RESET# XTAL1 XTAL2 Figure B-6 XC196MH 64-lead Shrink DIP Sdip Package X8XC196MH Figure B-7 XC196MH 84-lead Plcc Package Signal Descriptions Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Column Heading Description Name Table B-6. Signal DescriptionsTable B-5. Description of Columns of Table B-6 BCLK10 COMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD CCR0.1 CCR1.2Buswidth Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH PMODE.30 Slave programmingAuto programming Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Port Signals Alternate During Upon RESET# Table B-7. Definition of Status SymbolsTable B-8 XC196MC and MD Default Signal Conditions Functions RESET# Active WG3 WK1 NMI WK0 RESET#WG2 WK1 PWM0 WK0 Port Signals Table B-9 XC196MH Default Signal ConditionsRESET# Alternate During Upon Osc output Registers Page 8XC196MC, MH, x = Table C-1. Modules and Related RegistersCPU Table C-2. Register Name, Address, and Reset Status Xxxx EPA4TIME MD Xxxx EPA2TIME MC, MDXxxx EPA3TIME MC, MD Xxxx EPA5TIME MD 1FFD P7PIN MDXxxx P1REG MH P5REG MC, MD Usfr MC, MD Xxxx TIMER1TIMER2 Usfr MH Xxxx Watchdog Adcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 COMPxCON Comp xCON Address Table C-3 = 0-3 8XC196MC, MH For EPA capture/compare channels 0, 2 COMPxTIME Table C-3. COMPxTIME Addresses and Reset ValuesRegister Address Reset Value Comp xTIME Address EPAxCON EPAxCON Address Table C-4 = 0-1 8XC196MH = 0-3 8XC196MC x = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset Values = 0-3 8XC196MC = 0-5 8XC196MD EPAxTIME Table C-5. EPAxTIME Addresses and Reset ValuesEPA Timer Value EPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Freqcnt Freqgen Gencon Intmask OVRTM† INTMASK1 Intpend INTPEND1 Ffffh OnesregOnesreg One = 1 MH Table C-6. PxDIR Addresses and Reset ValuesPxDIR = 2, 5 M = 1 MH = 2, 5 Mx Table C-7. PxMODE Addresses and Reset ValuesPxMODE PIN7 PIN6 PIN5 PIN4 Port Table C-8. Special-function Signals for Ports 1, 2, 5Pin Special-function Signal 8XC196MC, MD Table C-9. PxPIN Addresses and Reset Values PxPIN PxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MH Table C-10. PxREG Addresses and Reset ValuesPxREG = 2-5 M Pimask Pimask Pipend Pipend PPW PPW150 Ppwvalue PSE PSWPSW PSW Ptssel Ptssrv Pwmcount Pwmperiod PWMxCONTROL PWM xCONTROL Address 1FB0H, 1FB2H 8XC196MH Data Received Bit SBUFxRXSBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH 8XC196MH Data to Transmit Bit SBUFxTXSbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH Stack Pointer 150 Stack Pointer SPxBAUD SPxCON SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxSTATUS T1CONTROL T1RELOAD Timer 1 Reload ValueT1RELOAD T2CONTROL 1F7EH TIMERxTimer Address 1F7AH Usfr 0AH WatchdogWatchdog WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Table C-11. Output Configuration Output Values Output Polarities WG x# Wgprotect Wgreload Register Mnemonic WSRByte Windows 00E0-00FFH 00C0-00FFH 00E0-00FFH 00C0-00FFH 0080-00FFH Location PWM0CONTROL 1FB0H 7DH T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2H PWM1CONTROL 1FB2H 7DH Zero ZeroregZeroreg Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14