Intel 8XC196MH, 8XC196MD, 8XC196MC manual Shral Arithmetic Right Shift Double

INSTRUCTION SET REFERENCE

Table A-6. Instruction Set (Continued)

Mnemonic			Operation						Instruction Format
SHRAL	ARITHMETIC RIGHT SHIFT DOUBLE-
	WORD. Shifts the destination double-word							SHRAL	lreg, #count
	operand to the right as many times as
								(00001110) (count) (lreg)
	specified by the count operand. The count
	may be specified either as an immediate							or
	value in the range of 0 to 15 (0FH), inclusive,							SHRAL	lreg, breg
	or as the content of any register (10H –
								(00001110) (breg) (lreg)
	0FFH) with a value in the range of 0 to 31
	(1FH), inclusive. If the original high order bit
	value was “0,” zeros are shifted in. If the							NOTES:	This instruction clears the
	value was “1,” ones are shifted in.
									sticky bit flag at the beginning
	Temp ← (COUNT)
									of the instruction. If at any time
	do while Temp ≠ 0								during the shift a “1” is shifted
	C ← Low order bit of (DEST)								into the carry flag and another
	(DEST) ← (DEST)/2								shift cycle occurs, the instruc-
	Temp ← Temp – 1								tion sets the sticky bit flag.
	end_while
									In this operation, (DEST)/2 rep-
			PSW Flag Settings						resents signed division.
		Z	N	C	V	VT	ST
		✓	✓	✓	0	—	✓
SHRB	LOGICAL RIGHT SHIFT BYTE. Shifts the
	destination byte operand to the right as many							SHRB	breg, #count
	times as specified by the count operand. The
								(00011000) (count) (breg)
	count may be specified either as an
								or
	immediate value in the range of 0 to 15
	(0FH), inclusive, or as the content of any							SHRB	breg, breg
	register (10H – 0FFH) with a value in the
								(00011000) (breg) (breg)
	range of 0 to 31 (1FH), inclusive. The left bits
	of the result are filled with zeros. The last bit
	shifted out is saved in the carry flag.							NOTES:	This instruction clears the
	Temp ← (COUNT)
									sticky bit flag at the beginning
	do while Temp ≠ 0								of the instruction. If at any time
	C ← Low order bit of (DEST)								during the shift a “1” is shifted
	(DEST) ← (DEST)/2								into the carry flag and another
	Temp ← Temp–1								shift cycle occurs, the instruc-
	end_while								tion sets the sticky bit flag.
									In this operation, (DEST)/2 rep-
			PSW Flag Settings
									resents unsigned division.
		Z	N	C	V	VT	ST
		✓	0	✓	0	—	✓

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