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Intel 8XC196MH, 8XC196MD, 8XC196MC manual bit System with Flash

Models: 8XC196MD 8XC196MH 8XC196MC

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8XC196MC, MD, MH USER’S MANUAL

Figure 15-18 and Figure 15-19 show sample circuits that use the address valid strobe mode. Fig- ure 15-18 shows a simple 8-bit system with a single flash. It is configured for the address valid strobe mode. This system configuration uses the ADV# signal as both the flash chip-select signal and the address-latch signal.

RD#

AD14:8

8XC196

AD7:0

ADV#

74AC		A7:0
373
LE

OE#

A14:8

D7:0

32K×8

Flash

(28F256)

A7:0

CS#

A3094-01

Figure 15-18. 8-bit System with Flash

15-28

Image 343

Intel 8XC196MH, 8XC196MD, 8XC196MC manual bit System with Flash

Contents

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’ Manual We Value Your Opinion Page 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Intel Corporation Contents Chapter Memory Partitions Contents 8XC196MC, MD, MH USER’S Manual Programming the Waveform Generator PWM Signals and RegistersFunctional Overview Programming the Frequency Generator Application ExampleChapter Event Processor Array EPA Chapter Minimum Hardware Considerations Chapter Programming the Nonvolatile Memory Appendix C Registers Glossary Index Figures 10-5 15-9 Ready Timing Diagram One Wait State 8XC196MH 15-21 Tables 11-12 16-7 Pmode Values Guide to This Manual Page Chapter Guide to this Manual Manual ContentsSpecial Operating Modes Assert and deassert Notational Conventions and TerminologyNumbers Related Documents Application Notes, Application Briefs, and Article Reprints Handbooks and Product InformationTitle Order Number MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/ExpressThis Page Left Intentionally Blank Guide to this Manual This Page Left Intentionally Blank Technical Support World Wide WebProduct Literature Page Architectural Overview Page Typical Applications Microcontroller FeaturesSIO PWM Features of the 8XC196Mx Product FamilyFunctional Overview OtpromRAM ROMPTS EPA PWM WDT SIO CPURegister File CPU ControlRegister Arithmetic-logic Unit Ralu Instruction Format Code ExecutionMemory Interface Unit Interrupt ServiceClock Circuitry Internal TimingState Times at Various Frequencies Internal PeripheralsSerial I/O SIO Port 1 I/O PortsWaveform Generator Event Processor Array EPA and Timer/CountersPulse-width Modulator PWM Frequency GeneratorAnalog-to-digital Converter Watchdog TimerReducing Power Consumption Testing the Printed Circuit BoardProgramming the Nonvolatile Memory Programming Considerations Page Restrictions Overview of the Instruction SETOperand Type Definitions Operand Type No. Signed Possible Values AddressingWord Operands BIT OperandsByte Operands SHORT-INTEGER OperandsDOUBLE-WORD Operands Integer OperandsFloating Point Operations LONG-INTEGER OperandsConverting Operands Conditional JumpsAddressing Modes Definition of Temporary Registers Direct AddressingImmediate Addressing Indirect AddressingShort-indexed Addressing Indexed AddressingIndirect Addressing with Autoincrement Indirect Addressing with the Stack PointerZero-indexed Addressing Long-indexed AddressingUsing Registers Assembly Language Addressing Mode SelectionsSoftware Standards and Conventions Linking Subroutines Addressing 32-bit OperandsSoftware Protection Features and Guidelines 8XC196MC, MD, MH USER’S Manual Memory Partitions Page External Devices Memory or I/O Memory PartitionsProgram and Special-purpose Memory Description Addressing Modes Program MemoryMemory Map DeviceInterrupt and PTS Vectors Special-purpose MemorySpecial-purpose Memory Addresses Reserved Memory LocationsSpecial-function Registers SFRs Chip Configuration Bytes CCBsSecurity Key Peripheral SFRs Memory-mapped SFRsSFRs EPA and Timer SFRsPeripheral SFRs 8XC196MC Port 2 SFRsPorts 2 and 7 SFRs Peripheral SFRs 8XC196MDSerial I/O Port SFRs Peripheral SFRs 8XC196MHPort 0 and 2 SFRs Port 1 SFRsAddress Register File Memory MapDevice and Hex Address Range Description Addressing Modes Register File Memory AddressesGeneral-purpose Register RAM Stack Pointer SPCPU SFRs CPU Special-function Registers SFRsAddress High Odd Byte Low Even Byte 00FFH Windowing8XC196MC,MD 02FFH 01FFHWSR Value for Peripherals Selecting a WindowWSR Bit Function Number10. Selecting a Window of the Upper Register File Addressing a Location Through a WindowPeripheral SFRs 11. Windows12. Windowed Base Addresses Base WSR Value WSR Value forUnsupported Locations Windowing Example 2.1 32-byte Windowing Example2.2 64-byte Windowing Example 2.3 128-byte Windowing Example?WSR Using the Linker Locator to Set Up a WindowThis listing shows the disassembled code LDB WSR, #12H Windowing and Addressing ModesPage Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals Interrupt Signals and RegistersInterrupt and PTS Control and Status Registers Ptssrv Interrupt Sources and PrioritiesPipend 1FBEH PtsselInterrupt Sources, Vectors, and Priorities Interrupt Controller PTS ServiceInterrupt Source Mnemonic Name Vector Priority Software Trap Special InterruptsExternal Interrupt Pin Unimplemented OpcodeWaveform Generator Protection Circuitry Multiplexed Interrupt SourcesFlow Diagram for the Ovrtm Interrupt Interrupt Latency End-of-PTS InterruptsSituations that Increase Interrupt Latency Standard Interrupt Latency Calculating LatencyStandard Interrupt Response Time PTS Interrupt Latency Programming the Interrupts PTS Mode Execution Time in State TimesExecution Times for PTS Cycles Standard and PTS Interrupts Bit Function Ptssel8XC196MC 8XC196MDCOMP2 MC, MD IntmaskCOMP2 EPA2 COMP1 EPA1 COMP3 COMP0 EPA0 Ovrtm Bit Mnemonic Interrupt Standard VectorNMI Extint SPI COMP3 EPA3 COMP4 EPA4 RI1 RI0 TI1 TI0 INTMASK1NMI Extint NMI Extint EPA58XC196MC 8XC196MD PimaskBit Function Number Mnemonic Pimask Modifying Interrupt PrioritiesOVRTM1 Standard and PTS Interrupts Determining the Source of an Interrupt Intpend 10. Interrupt Pending Intpend RegisterINTPEND1 11. Interrupt Pending 1 INTPEND1 RegisterPipend 12. Peripheral Interrupt Pending Pipend RegisterPipend Initializing the PTS Control BlocksSpecifying the PTS Count Ptssrv 14. PTS Service Ptssrv RegisterSingle Transfer Mode Selecting the PTS ModePtscon Ptsdst Ptscb + PTS Single Transfer Mode Control BlockPtsdst H Ptsdst L Ptssrc H Ptssrc L Ptscon Ptscount Register Location FunctionStandard and PTS Interrupts Single Transfer Mode Ptscb Block Transfer ModeBlock Transfer Mode Ptscb Ptsblock Ptscb + PTS Block Transfer Mode Control Block5 A/D Scan Mode PTS A/D Scan Mode Control Block Address Contents A/D Scan Mode Command/Data Table5.2 A/D Scan Mode Example 5.1 A/D Scan Mode CyclesPtscount = 04H Command/Data Table ExampleA/D Scan Mode Ptscb Example PTSPTR2 H = 1FH PTSPTR2 L = AAHSerial I/O Modes 5.3 A/D Scan Mode Example10. Command/Data Table Example 11. A/D Scan Mode Ptscb ExampleSA1 SA0 MAJ PTS Serial I/O Mode Control Block 1 8XC196MC, MDPtsvec SA0 † BaudEpareg SA18XC196MC, MD, MH USER’S Manual Port Mask Register PTS Serial I/O Mode Control Block 2 8XC196MC, MDPort Address Pointer high byte PTSCON1 DataRpar 8XC196MC, MD Register Location Function PTS Serial I/O Mode Control BlockPortreg 8XC196MC, MD, MH USER’S Manual PTSCB1 PTSCB2 13. Ssio Transmit Mode PTSCBsTxddone = 23. Synchronous SIO Receive Timing Synchronous SIO Receive Mode ExampleClrb Rxddone 14. Ssio Receive Mode PTSCBsStandard and PTS Interrupts Rxddone = 25. Asynchronous SIO Transmit Timing 15. Asio Transmit Mode PTSCBs Standard and PTS Interrupts End-Of-PTS Interrupt Save Critical Data Is PTS 27. Asynchronous SIO Receive Timing Asynchronous SIO Receive Mode ExampleSamptime = 01H 16. Asio Receive Mode PTSCBsPortreg H = 1FH P2PIN Standard and PTS Interrupts End-Of-PTS Interrupt Ports Page Device I/O Ports I/O Ports OverviewPort Bits Type Direction Associated Peripherals INPUT-ONLY Ports 1 MC, MD only Standard Input-only Port PinsP1PIN MC, MD Standard Input-only Port OperationInput-only Port Registers 1FDAH MHBidirectional Ports 1 MH ONLY, 2, 5, and 7 MD only Standard Input-only Port ConsiderationsPort Pin Special-function Associated Signals Bidirectional Port PinsBidirectional Port Control and Status Registers Bidirectional Port OperationPorts Bidirectional Port Structure Logic Table for Bidirectional Ports in I/O Mode Bidirectional Port Pin ConfigurationsSfdir 8XC196MC, MD, MH USER’S Manual Control Register Values for Each Configuration Bidirectional Port Pin Configuration ExamplePort Configuration Example HZ1 Bidirectional Port ConsiderationsP5.1/INST 12. Ports 3 and 4 Control and Status Registers Ports 3 and 4 PinsPort Pins Special-function Bidirectional Ports 3 and 4 ADDRESS/DATA BUSAddress/Data Bus Ports 3 and 4 Structure Bidirectional Ports 3 and 4 Address/Data Bus Operation13. Logic Table for Ports 3 and 4 as Open-drain I/O Using Ports 3 and 4 as I/ODesign Considerations for Ports 3 Standard OUTPUT-ONLY Port15. Output-only Port Control Register Configuring Output-only Port Pins14. Standard Output-only Port Pins Output-only Port OperationOP1 OP0 Reset State 0000HWgoutput Port Address 1FC0HWgoutput Port Reset State 0000HPage Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block DiagramSerial Port Signals Serial I/O Port Signals and RegistersSerial Port Control and Status Registers P1PIN 1F9FH P1DIR 1F9BHP1REG 1F9DH Serial Port Modes Mode Synchronous Modes Modes 0Mode 0 Timing Asynchronous Modes Modes 1, 2, Serial Port Frames for Mode Multiprocessor Communications Mode 2 and 3 TimingsSP xCON Address 1F83H, 1F8BH = 0-1 8XC196MH Configuring the Serial Port PinsProgramming the Serial Port Programming the Control RegisterBit Function BV9 BV8 Programming the Baud Rate and Clock SourceClksrc BV7Bclk Baudvalue =E82BH SPxBAUD Values When Using XTAL1 at 16 MHzEnabling the Serial Port Interrupts 80CFHRPE/RB8 TXE Determining Serial Port StatusRPE/RB8 8XC196MC, MD, MH USER’S Manual Frequency Generator Page Chapter Frequency Generator Frequency Generator Control and Status Registers Frequency Generator SignalPort Frequency Freqgen Configuring the OutputProgramming the Frequency Generator Programming the FrequencyApplication Example Determining the Current Value of the Down-counterFreqcnt Frequency Generator 0FAH Xmitbuf Dsb Bufsize Block of data to send Shiftreg Stb temp,freqgen0 Into freq gen Frequency Generator Page Waveform Generator Page Waveform Generator Functional Overview Chapter Waveform GeneratorWaveform Generator Block Diagram Waveform Generator Signals Waveform Generator Signals and RegistersWaveform Generator Control and Status Registers Timebase Generator Waveform Generator OperationControl and Protection Circuitry Phase Driver ChannelsProtection Circuitry Register Buffering and SynchronizationOperating Modes Step Center-aligned Modes Edge-aligned Modes Register UpdatesEvent Mode Operation in Center-aligned and Edge-aligned ModesCenter-aligned Modes Counter Operation Center-aligned ModesCenter-aligned Modes Output Operation Edge-Aligned Modes Edge-aligned Modes Counter Operation Output Configuration Configuring the OutputsProgramming the Waveform Generator OP1 Wgoutput Waveform GeneratorOP1 OP0 Sync PE7 PE68XC196MC, MD, MH USER’S Manual 8XC196MC, MD 8XC196MH Bit Function Number Mnemonic WgprotectF0H E0H150 Reload Specifying the Carrier Period and Duty CycleWgreload Reload1FC2H,1FC4H,1FC6H Wgcomp AddressDT7 DT6 DT5 DT4 DT9 DT8 DT3 DT2 DT1 DT0 WgcontrolWgcounter = Wgreload Xxxxh Determining the Waveform GENERATOR’S StatusEnabling the Waveform Generator Interrupts WgcounterWgcomp Design ConsiderationsDead Time and Duty Cycle Wgcount WGCOUNT=Programming Example Ph3 Dsw P6.4,5 config Waveform Generator Temp1,WGOUTPUT0 Now store it Ret Demo board PI interrupt Page Pulse-width Modulator Page PWM Functional Overview Chapter PULSE-WIDTH ModulatorPWM Signals PWM Signals and RegistersPWM Control and Status Registers PWM OperationPEx Pin Output E6H Programming the Frequency and PeriodFFH Pwmperiod PWM Output Frequencies FpwmPwmperiod + Programming the Duty CycleReading the Current Value of the Down-counter Sample CalculationsPWM xCONTROL Address 10-3 Pwmcount PWM Output Alternate Port Function PWM Output Enabled WhenEnabling the PWM Outputs PWM Output Alternate FunctionsWaveform Generator Output Configuration Wgoutput Register Generating Analog Outputs D/A Buffer Block DiagramEvent Processor Array EPA Page COMP30 EPA Functional OverviewEPA Channels Device Capture/Compare Channels Compare-only ChannelsEPA and Timer/Counter Signals EPA and TIMER/COUNTER Signals and RegistersEPA Control and Status Registers P1PIN 1FA9H P0PIN 1FA8HT1RELOAD TIMER/COUNTER Functional OverviewTIMER1 1F7AH TIMER2 1F7EHEPA Timer/Counters Quadrature Clocking Modes Cascade Mode Timer 2 OnlyT1DIR State of Xinternal State of Yinternal Count DirectionEPA Channel Functional Overview Quadrature Mode Timing and CountA Single EPA Capture/Compare Channel Operating in Capture ModeEPA Simplified Input-capture Structure EPAxCON.0 Action Taken When a Valid Edge OccursOverwrite Bit Status Action Taken When a Valid Edge Occurs EPA OverrunsPreventing EPA Overruns Operating in Compare ModeGenerating a Low-speed PWM Output Generating the Highest-speed PWM Output Configuring the EPA and Timer/Counter Signals Programming the EPA and TIMER/COUNTERSProgramming the Timers T1CONTROL Prescaler Divisor Resolution †Clock Source Direction Source T2CONTROL Prescaler Resolution †Mode WGR ROT ON/RT Example EPA Control Register Settings for Channels 1, 3, orProgramming the Capture/Compare Channels = 0, 2 = 1, 3 Capture Mode EventCompare Mode Action EPAxCON = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MDFor EPA capture/compare channels 1, 3 EPA xCON Address= 0, 2 For EPA capture/compare channels 0, 2Compare Mode RT Capture Mode onWGR ROT = 0-3 8XC196MC, MH = 0-5 8XC196MD Reset State 00HProgramming the Compare-only Channels Comp xCON AddressEnabling the EPA Interrupts Determining Event Status Analog-to-digital Converter PageNum-38 Angnd 12.1 A/D Converter Functional OverviewA/D Control and Status Registers 12.2 A/D Converter Signals and RegistersA/D Converter Pins Port Pin Signal DescriptionP1PIN MC,MD 12.3 A/D Converter OperationProgramming the A/D Converter Adtest Programming the A/D Test RegisterOFF1 OFF0 Adresult Write Programming the A/D Time RegisterAdtime Programming the A/D Command RegisterACH3 ACH2 ACH1 ACH0 AdcommandM1 M0 Mode Enabling the A/D InterruptAdresult Read Determining A/D Status and Conversion ResultsADRLT90 Idealized A/D Sampling Circuitry Designing External Interface CircuitryMinimizing the Effect of High Input Source Resistance Suggested A/D Input Circuit Using Mixed Analog and Digital Inputs Understanding A/D Conversion Errors12-14 Ideal A/D Conversion Characteristic 10. Actual and Ideal A/D Conversion Characteristics 12-17 11. Terminal-based A/D Conversion Characteristic Minimum Hardware Considerations Page RESET# Minimum Required SignalsMinimum Connections 13.1.2 I/O Port Pin Connections I/O Port Configuration GuidePort Where to Find Configuration Information Unused InputsMinimum Hardware Connections Noise Protection Tips Applying and Removing PowerOn-chip Oscillator Circuit ON-CHIP Oscillator CircuitryExternal Crystal Connections External Clock Connections Using AN External Clock SourceReset Timing Sequence Resetting the DeviceDRO GenconRsts DR0 RstsInternal Reset Circuitry Generating an External Reset10. Minimum Reset Circuit Generating Wait States Issuing the Reset RST InstructionEnabling the Watchdog Timer Issuing an Illegal Idlpd Key Operand1EH A1H Selecting the Watchdog Reset Interval 8XC196MH onlyFirst Byte Second Byte Reset Interval 1EH E1HPage Special Operating Modes Page Clkout Special Operating Mode Signals and RegistersOperating Mode Control Signals Port Pin Signal Type DescriptionCCR0 Operating Mode Control and Status RegistersPort Pin Signal Type Description Name ONCE#P1REG MH 1F9DH Reducing Power ConsumptionP1MODEMH P7MODEMD 1FD1HClock Control During Power-saving Modes Idle ModeEnabling and Disabling Powerdown Mode Powerdown ModeDriving the VPP Pin Low Entering Powerdown ModeExiting Powerdown Mode Generating a Hardware ResetAsserting the External Interrupt Signal Selecting R1 and C1 External RC CircuitTypical Voltage on the VPP Pin While Exiting Powerdown Once Mode Reserved Test Modes Page Interfacing with External Memory Page ADV# External Memory Interface Signals and RegistersExternal Memory Interface Signals Signal Port Pin Type Description NameCCR1.2 Buswidth Bytes AccessedBHE# AD0 CCR0.1EA# Signal Port PinWR# Register Address Description Mnemonic External Memory Interface RegistersWRH# WRL#P5REG = 11XX Xxxxb Chip Configuration Registers and Chip Configuration BytesBHE#/WRH# † 15-6 IRC2 IRC1 IRC0 CCR0LOC1 LOC0 IRC1 IRC0 ALE BW0 LOC1 LOC0ALE CCR0BW1 BW0 WDE BW1 IRC2 CCR1WDE CCR1 BUS Width and MultiplexingMultiplexing and Bus Width Options Buswidth Timing Diagram 8XC196MC, MD Symbol Definition Buswidth Signal Timing DefinitionsTiming Requirements for Buswidth 15.3.2 16-bit Bus Timings Timings for 16-bit Buses 15.3.3 8-bit Bus Timings Timings for 8-bit Buses Wait States Ready Control15-18 Ready Timing Diagram One Wait State 8XC196MC, MD Address Valid to Ready Setup BUS-CONTROL Modes Bus-control Mode Bus-control Signals CCR0.3 CCR0.2Bus-control Modes BHE# WR# AD0 Standard Bus-control ModeALE OE# WE# RD# WR# CS#Eprom RAM Buswidth CS#OE# WE# RD# WR# 14. Write Strobe Mode Write Strobe ModeOE# OE# WE# RD# WRH# WRL# 15 -bit System with Writes to Byte-wide RAMs16. Address Valid Strobe Mode Address Valid Strobe Mode18 -bit System with Flash OE# RD# Eprom20. Timings of Address Valid with Write Strobe Mode Address Valid with Write Strobe ModeWE# CS# System BUS AC Timing SpecificationsVCC Buswidth WRH# WRL# CS#22. System Bus Timing AC Timing Definitions Explanation of AC SymbolsAC Timing Symbol Definitions Signals External Memory Systems Must Meet These SpecificationsAddress Setup to ALE/ADV# Low Microcontroller Meets These Specifications15-35 Page Programming Nonvolatile Memory Page Programming Methods Programming the Nonvolatile MemoryOtprom Memory MAP Address Range Description Hex Security FeaturesControlling Access to Internal Memory C196Mx Otprom Memory MapRead Protect Write Protect Protection Status Controlling Access to the Otprom During Normal OperationMemory Protection for Normal Operating Mode Controlling Access to the Otprom During Programming ModesSecurity Key Memory Protection Options for Programming ModesPccb CCB Controlling Fetches from External Memory Usfr Uprom Programming Values and Locations for Slave ModeTo set this bit Write this value To this location BitBitFunction Number Mnemonic Programming Pulse WidthPpwvalue PPWPpwvalue = Modified QUICK-PULSE AlgorithmExample Ppwvalue Calculations 8XC196MC, MD 8XC196MH Two 250-µs pulses requiredModified Quick-pulse Algorithm Special Program Port Pin Programming Mode PinsPACT# PROG#AINC# CpverEntering Programming Modes Selecting the Programming ModePmode Values Power-up Sequence Power-up and Power-down SequencesPower-down Sequence Reading the Signature Word and Programming Voltages Slave Programming ModeLocation Value Slave Programming Circuit and Memory MapDevice Signature Word and Programming Voltages Device Signature Word Programming VCCOperating Environment Slave Programming Mode Memory MapDescription Address Comments LOC1 LOC0 IRC1 IRC0 WDE BW1 IRC2 CCR1, CCR0Bit Mnemonic Function Slave Programming Routines Address/Command Decoding Routine Program Word Routine Program Word Waveform 10. Dump Word Routine 10. Timing Mnemonics Timing MnemonicsMnemonicDescription Auto Programming Circuit and Memory Map Auto Programming ModeMnemonic Description 12. Auto Programming Circuit 11 XC196MC/MD Auto Programming Memory Map Address Internal Address Using Output fromAddress Internal Address Using Auto Programming Routine13. Auto Programming Routine Auto Programming Procedure Pccb and Uprom Programming 8XC196MH only ROM-dump Mode14. Pccb and Uprom Programming Circuit PMODE30 0DH Pins Pccb Programming Uprom ProgrammingRUN-TIME Programming 13. Pccb and Uprom Programming Values15. Run-time Programming Code Example Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left HalfTable A-1. Opcode Map Right Half Value of Bits Shifted Off Table A-2. Processor Status Word PSW FlagsInstruction Quotient Stored Flag Set if Quotient is Symbol Description Table A-4. PSW Flag Setting SymbolsInstruction Jumps to Destination if Continues if Variable Description Table A-5. Operand VariablesC V VT ST PSW Flag SettingsTable A-6. Instruction Set Mnemonic OperationDest ← Dest and SRC Instruction FormatAndb Count PTRS, CntregDest Count ← Cntreg Loop Srcptr ← Ptrs DstptrDstptr ← Srcptr Ptrs ← Srcptr + Count ← CountClear BYTE. Clears the value Mnemonic Operation Instruction Format Dest MOD SRC ← Dest MOD SRCDjnzw Decrement and Jump if not Zero Djnz Decrement and Jump if not ZeroEXT SIGN-EXTEND Integer Into Long Dpts Disable Peripheral TransactionEpts Enable Peripheral Transaction EptsExtb SIGN-EXTEND SHORT-INTEGER Into Increment BYTE. Increments the value Byte operand by JGE Jump if Signed Greater than or JLE Jump if Signed Less than or Equal Negative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear Jnvt Jump if OVERFLOW-TRAP Flag is JVT Jump if OVERFLOW-TRAP Flag is SET Load Byte SIGN-EXTENDED. Sign Mulb MULMulub MuluSRC, Dest Integer operandDest ← Dest or SRC Dest ← not DestPSW/INTMASK ← SP INTMASK1/WSR ← SPSP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ←Scall Wreg, #count SHR Range of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double Skip Shrl Logical Right Shift DOUBLE-WORDSUB Rightmost operandSubcb Subtract Bytes with Borrow DEST, SRC SubbSubc Subtract Words with Borrow DEST, SRC Subc× Offset + Tbase = Dest Index and #MASK = OffsetTijmp TBASE, INDEX, #MASK Dest ← Dest XOR SRC XORDecb Extb Incb Shrb Shlb Shrab Table A-7. Instruction OpcodesHex Code Instruction Mnemonic Clrb Notb NegbHex Code Hex Code 8XC196MC, MD, MH USER’S Manual EF Lcall Dpts EptsDIV/DIVB/MUL/MULB Note Arithmetic Group Direct Immediate Indirect Indexed Mnemonic Table A-8. Instruction Lengths and Hexadecimal OpcodesSubc Subcb Logical Direct Immediate Indirect Jump Direct Stack Direct Immediate Indirect Indexed MnemonicOpcode Length Data DirectLength Opcode Call Direct Immediate Indirect Indexed MnemonicConditional Jump Direct Immediate Mnemonic Direct Immediate Indirect Shift Mnemonic Direct Immediate Indirect IndexedSpecial Mnemonic Direct Immediate Indirect PTSMem Reg Table A-9. Instruction Execution Times in State TimesArithmetic Group Indirect Normal Autoinc Short Long Reg MemDIV Divb Divu Divub Mnemonic Direct Immed Normal Autoinc Short Long Reg MemLogical Normal Autoinc Short Stack Register IndirectReg Mem Ljmp Sjmp Tijmp Autoinc Short Long RegLDB Ldbse Ldbze STB XCH Xchb Autoinc Short LongNormal Autoinc Short Long Call Memory Indirect Indexed Mnemonic DirectConditional Jump Mnemonic NOP RST Setc Skip Shift Mnemonic DirectIndirect Indexed Clrc Clrvt IdlpdPage Signal Descriptions Page New Name Signal Name ChangesFunctional Groupings of Signals Table B-1. Signal Name ChangesTable B-2 XC196MC Signals Arranged by Functional Categories U8XC196MC Figure B-1 XC196MC 64-lead Shrink DIP Sdip PackageX8XC196MC Figure B-2 XC196MC 84-lead Plcc PackageFigure B-3 XC196MC 80-lead Shrink EIAJ/QFP Package P7.7/FREQOUT Table B-3 XC196MD Signals Arranged by Functional CategoriesX8XC196MD Figure B-4 XC196MD 84-lead Plcc PackageFigure B-5 XC196MD 80-lead Shrink EIAJ/QFP Package EA# Extint NMI ONCE# RESET# XTAL1 XTAL2 Table B-4 XC196MH Signals Arranged by Functional CategoriesP2.7/SCLK1#/BCLK1 X8XC196MH Figure B-6 XC196MH 64-lead Shrink DIP Sdip PackageFigure B-7 XC196MH 84-lead Plcc Package Figure B-8 XC196MH 80-lead Shrink EIAJ/QFP Package Signal DescriptionsTable B-5. Description of Columns of Table B-6 Table B-6. Signal DescriptionsColumn Heading Description Name BCLK10 Buswidth CCR0.1 CCR1.2COMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7MC, MD Command that invoked the power-saving mode System using a clip-on emulator P5.7/BUSWIDTH Auto programming Slave programmingPMODE.30 Programming Start SCLK10# Shift Clock 0 MH only Default Conditions Functions RESET# Active Table B-7. Definition of Status SymbolsTable B-8 XC196MC and MD Default Signal Conditions Port Signals Alternate During Upon RESET#PWM0 WK0 NMI WK0 RESET#WG2 WK1 WG3 WK1Alternate During Upon Table B-9 XC196MH Default Signal ConditionsRESET# Port SignalsOsc output Registers Page CPU Table C-1. Modules and Related Registers8XC196MC, MH, x = Table C-2. Register Name, Address, and Reset Status Xxxx EPA5TIME MD Xxxx EPA2TIME MC, MDXxxx EPA3TIME MC, MD Xxxx EPA4TIME MDP5REG MC, MD P7PIN MDXxxx P1REG MH 1FFDUsfr MH Xxxx Watchdog Xxxx TIMER1TIMER2 Usfr MC, MDAdcommand Adresult Read Adresult Write Adtest Adtime CCR0 ALE CCR1 IRC2 IRC1 IRC0 Comp xCON Address Table C-3 = 0-3 8XC196MC, MH COMPxCONFor EPA capture/compare channels 0, 2 Comp xTIME Address Table C-3. COMPxTIME Addresses and Reset ValuesRegister Address Reset Value COMPxTIMEEPAxCON = 0-3 8XC196MC x = 0-5 8XC196MD EPAxCON Address Table C-4 = 0-1 8XC196MH= 0-3 8XC196MC = 0-5 8XC196MD Table C-4. EPAxCON Addresses and Reset ValuesEPAxTIME = 0-1 8XC196MH x = 0-3 8XC196MC x = 0-5 8XC196MD Table C-5. EPAxTIME Addresses and Reset ValuesEPA Timer Value EPAxTIMEFreqcnt Freqgen Gencon OVRTM† IntmaskINTMASK1 Intpend INTPEND1 One OnesregOnesreg Ffffh= 2, 5 M Table C-6. PxDIR Addresses and Reset ValuesPxDIR = 1 MHPIN7 PIN6 PIN5 PIN4 Table C-7. PxMODE Addresses and Reset ValuesPxMODE = 1 MH = 2, 5 Mx8XC196MC, MD Table C-8. Special-function Signals for Ports 1, 2, 5Pin Special-function Signal PortPxPIN Table C-9. PxPIN Addresses and Reset Values= 2-5 M Table C-10. PxREG Addresses and Reset ValuesPxREG PxREG = 2-5 8XC196MC = 2-5, 7 8XC196MD x = 1-5 8XC196MHPimask Pimask Pipend Pipend PPW150 Ppwvalue PPWPSW PSWPSE PSW Ptssel Ptssrv Pwmcount Pwmperiod PWM xCONTROL Address 1FB0H, 1FB2H PWMxCONTROLSBUFxRX Address 1F80H, 1F88H = 0-1 8XC196MH SBUFxRX8XC196MH Data Received Bit Sbuf xTX Address 1F82H, 1F8AH = 0-1 8XC196MH SBUFxTX8XC196MH Data to Transmit Bit 150 Stack Pointer Stack PointerSPxBAUD SPxCON Address 1F83H, 1F8BH = 0-1 8XC196MH SPxCONSPxSTATUS T1CONTROL T1RELOAD Timer 1 Reload ValueT1RELOAD T2CONTROL Timer Address 1F7AH TIMERx1F7EH Usfr Watchdog Watchdog0AH WGCOMPx Wgcontrol Wgcounter Wgoutput Port Wgoutput Waveform Generator Wgoutput Waveform Generator Output Values Output Polarities WG x# Table C-11. Output ConfigurationWgprotect Wgreload 00E0-00FFH 00C0-00FFH WSRByte Windows Register Mnemonic00E0-00FFH 00C0-00FFH 0080-00FFH Location PWM1CONTROL 1FB2H 7DH T2CONTROL 1F7CH 7BH 00FCH 3DH 1EH TIMER1 † 1F7AH 00FAH1EH 00FAH TIMER2 † 1F7EH 7BH 00FEH 3DH WGCOMP1 1FC2H PWM0CONTROL 1FB0H 7DHZeroreg ZeroregZero Page Glossary Page Glossary Characteristic DOUBLE-WORD LONG-INTEGER LSB Otprom PTS PWM SFR Special interrupt WDT Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14