Texas Instruments MSP430x1xx manuals
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Texas Instruments MSP430x1xx Manual
432 pages 1.55 Mb
Preface 3 About This Manual Related Documentation From Texas Instruments FCC Warning Notational Conventions 4 Glossary5 Register Bit ConventionsRegister Bit Accessibility and Initial Condition 7 13 37 !113 "# "131 " ""153 " $" %161 &'""169 () ""193 ("*201 + 211 ,)235 ,261 !) " - !)262 13.1 USART Introduction: UART Mode264 13.2 USART Operation: UART Mode274 USART Operation: UART Mode 13-16 USART Peripheral Interface, UART Mode 276 Typical Baud Rates and ErrorsTable 132.Commonly Used Baud Rates, Baud Rate Data, and Errors 277 13.2.7 USART InterruptsUSART Transmit Interrupt Operation Figure 1310. Transmit Interrupt Operation 278 USART Receive Interrupt OperationFigure 1311.Receive Interrupt Operation 279 Receive-Start Edge Detect Operation280 Figure 1312. Glitch Suppression, USART Receive Not StartedFigure 1313. Glitch Suppression, USART Activated 281 13.3 USART Registers: UART ModeTable 133.USART0 Control and Status Registers Table 134.USART1 Control and Status Registers 282 UxCTL, USART Control Register283 UxTCTL, USART Transmit Control Register284 UxRCTL, USART Receive Control Register285 UxBR0, USART Baud Rate Control Register 0UxBR1, USART Baud Rate Control Register 1 UxMCTL, USART Modulation Control Register 286 UxRXBUF, USART Receive Buffer RegisterUxTXBUF, USART Transmit Buffer Register 287 ME1, Module Enable Register 1ME2, Module Enable Register 2 288 IE2, Interrupt Enable Register 2289 IFG2, Interrupt Flag Register 2 Chapter 14 292 !)"-293 14.1 USART Introduction: SPI Mode295 14.2 USART Operation: SPI Mode304 14.3 USART Registers: SPI ModeTable 141.USART0 Control and Status Registers Table 142.USART1 Control and Status Registers 305 UxCTL, USART Control Register306 UxTCTL, USART Transmit Control Register307 UxRCTL, USART Receive Control Register308 UxBR0, USART Baud Rate Control Register 0UxBR1, USART Baud Rate Control Register 1 UxMCTL, USART Modulation Control Register 309 UxRXBUF, USART Receive Buffer RegisterUxTXBUF, USART Transmit Buffer Register 310 ME1, Module Enable Register 1ME2, Module Enable Register 2 311 IE2, Interrupt Enable Register 2313 IFG2, Interrupt Flag Register 2 Chapter 15 315 !) " - . 316 15.1 I2C Module Introduction318 15.2 I2C Module Operation334 15.3 I2C Module RegistersThe I2C module registers are listed in Table 154. Table 154.I2C Registers 335 U0CTL, USART0 Control Register-I2C Mode336 I2CTCTL, I2C Transmit Control Register337 I2CDCTL, I2C Data Control Register338 I2CDRW, I2CDRB, I2C Data RegisterI2CNDAT, I2C Transfer Byte Count Register 339 I2CPSC, I2C Clock Prescaler Register340 I2CSCLH, I2C Shift Clock High RegisterI2CSCLL, I2C Shift Clock Low Register 341 I2COA, I2C Own Address Register, 7-Bit Addressing ModeI2COA, I2C Own Address Register, 10-Bit Addressing Mode 342 I2CSA, I2C Slave Address Register, 7-Bit Addressing ModeI2CSA, I2C Slave Address Register, 10-Bit Addressing Mode 343 I2CIE, I2C Interrupt Enable Register344 I2CIFG, I2C Interrupt Flag Register345 I2CIV, I2C Interrupt Vector Register347 ,)359 )(.387 )(/388 18.1 ADC10 Introduction390 18.2 ADC10 Operation410 18.3 ADC10 RegistersThe ADC10 registers are listed in Table 183. Table 183.ADC10 Registers 411 ADC10CTL0, ADC10 Control Register 0413 ADC10CTL1, ADC10 Control Register 1414 ADC10AE, Analog (Input) Enable Control Register415 ADC10MEM, Conversion-Memory Register, Binary FormatADC10MEM, Conversion-Memory Register, 2s Complement Format 416 ADC10DTC0, Data Transfer Control Register 0417 ADC10DTC1, Data Transfer Control Register 1ADC10SA, Start Address Register for Data Transfer 419 ().
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