Texas Instruments MSP430x1xx manual Basic Clock Module Operation

Basic Clock Module Operation

4.2 Basic Clock Module Operation

After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~800 kHz (see device-specific datasheet for parameters) and ACLK is sourced from LFXT1 in LF mode.

Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic clock module. See Chapter System Resets, Interrupts and Operating Modes. The DCOCTL, BCSCTL1, and BCSCTL2 registers configure the basic clock module

The basic clock can be configured or reconfigured by software at any time during program execution, for example:

BIS.B	#RSEL2+RSEL1+RSEL0,&BCSCTL1	;
BIS.B	#DCO2+DCO1+DCO0,&DCOCTL	;	Set max DCO frequency

4.2.1Basic Clock Module Features for Low-Power Applications

Conflicting requirements typically exist in battery-powered MSP430x1xx applications:

-Low clock frequency for energy conservation and time keeping

-High clock frequency for fast reaction to events and fast burst processing capability

The basic clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals: ACLK, MCLK, and SMCLK. For optimal low-power performance, the ACLK can be configured to oscillate with a low-power 32,786-Hz watch crystal, providing a stable time base for the system and low power stand-by operation. The MCLK can be configured to operate from the on-chip DCO that can be only activated when requested by interrupt-driven events. The SMCLK can be configured to operate from a crystal or the DCO, depending on peripheral requirements. A flexible clock distribution and divider system is provided to fine tune the individual clock requirements.

4-4 Basic Clock Module