Texas Instruments MSP430x1xx manual Eint, Incd

Instruction Set

* EINT	Enable (general) interrupts
Syntax	EINT
Operation	1 → GIE
	or
	(0008h .OR. SR −> SR / .src .OR. dst −> dst)
Emulation	BIS	#8,SR
Description	All interrupts are enabled.
	The constant #08h and the status register SR are logically ORed. The result
	is placed into the SR.
Status Bits	Status bits are not affected.
Mode Bits	GIE is set. OSCOFF and CPUOFF are not affected.
Example	The general interrupt enable (GIE) bit in the status register is set.

;Interrupt routine of ports P1.2 to P1.7

;P1IN is the address of the register where all port bits are read. P1IFG is the address of

;the register where all interrupt events are latched.

;
	PUSH.B	&P1IN
	BIC.B	@SP,&P1IFG	; Reset only accepted flags
	EINT		; Preset port 1 interrupt flags stored on stack
			; other interrupts are allowed
	BIT	#Mask,@SP
	JEQ	MaskOK	; Flags are present identically to mask: jump
	......
MaskOK	BIC	#Mask,@SP
	......
	INCD	SP	; Housekeeping: inverse to PUSH instruction
			; at the start of interrupt subroutine. Corrects
			; the stack pointer.
	RETI

Note: Enable Interrupt

The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable.

3-40 RISC 16−Bit CPU