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Texas Instruments MSP430x1xx manual Jne, Jnz

Models: MSP430x1xx

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Instruction Set

JNE	Jump if not equal
JNZ	Jump if not zero
Syntax	JNE	label
	JNZ	label
Operation	If Z = 0: PC + 2 ⋅ offset −> PC
	If Z = 1: execute following instruction
Description	The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset
	contained in the instruction LSBs is added to the program counter. If Z is set,
	the next instruction following the jump is executed.
Status Bits	Status bits are not affected.
Example	Jump to address TONI if R7 and R8 have different contents.
	CMP	R7,R8	; COMPARE R7 WITH R8
	JNE	TONI	; if different: jump
	......		; if equal, continue

RISC 16−Bit CPU

3-51

Image 87

Texas Instruments MSP430x1xx manual Jne, Jnz

Contents

User’s Guide Products Applications Important NoticePreface Glossary Register Bit Conventions Register Bit Accessibility and Initial ConditionPage Introduction Risc 16-Bit CPU Basic Clock ModuleFlash Memory Controller Supply Voltage Supervisor TimerA Watchdog TimerUsart Peripheral Interface, SPI Mode 18 ADC10 Chapter Flexible Clock System Architecture−1. MSP430 Architecture Embedded EmulationAddress Space Flash/ROM2 RAM Peripheral Modules Special Function Registers SFRsMemory Organization 6Introduction Chapter −1. Power-On Reset and Power-Up Clear Schematic System Reset and Initialization−2. POR Timing Power-On Reset POR−3. Brownout Timing Brownout Reset BORSoftware Initialization Device Initial Conditions After System Reset−4. Interrupt Priority InterruptsNon-Maskable Interrupts NMI Reset/NMI Pin−5. Block Diagram of Non-Maskable Interrupt Sources Oscillator Fault Flash Access ViolationMaskable Interrupts Example of an NMI Interrupt HandlerInterrupt Acceptance Interrupt ProcessingInterrupt Nesting Return From Interrupt−1. Interrupt Sources,Flags, and Vectors Interrupt VectorsOperating Modes −10. MSP430x1xx Operating Modes For Basic Clock System Mode CPU and Clocks StatusExtended Time in Low-Power Modes Entering and Exiting Low-Power ModesPrinciples for Low-Power Applications Connection of Unused Pins−2. Connection of Unused Pins 18System Resets, Interrupts, and Operating Modes Chapter CPU Introduction −1. CPU Block Diagram Program Counter PC CPU Registers−3. Stack Pointer Stack Pointer SPStatus Register SR −1. Description of Status Register BitsBit Description Register Constant Remarks Constant Generator Registers CG1 and CG2−2. Values of Constant Generators CG1, CG2 Constant Generator − Expanded Instruction Set−7. Register -Byte/Byte-Register Operations General−Purpose Registers R4 R15As/Ad Addressing Mode Syntax Description Addressing Modes−3. Source/Destination Operand Addressing Modes Register Mode −4. Register Mode DescriptionAssembler Code Content of ROM −5. Indexed Mode Description Indexed Mode−6. Symbolic Mode Description Symbolic Mode−7. Absolute Mode Description Absolute Mode−8. Indirect Mode Description Indirect Register Mode−9. Indirect Autoincrement Mode Description Indirect Autoincrement Mode−10.Immediate Mode Description Immediate ModeInstruction Set Double-Operand Format I Instructions −11. Double Operand InstructionsMnemonic Reg Operation Status Bits −12.Single Operand Instructions Single-Operand Format II InstructionsJumps −13.Jump InstructionsMnemonic Reg, D-Reg Operation ADC.B ADC.WADD.B ADD.WADDC.B ADDC.WAND.B AND.WBIC.B BIC.WBIS.B BIS.WBIT.B BIT.WBR, Branch Call CLR.B Clrc Clrn Clrz CMP.B CMP.WDADC.B DADD.B DADD.WDEC.B −12. Decrement OverlapDECD.B Dint Disable InterruptIncd EintINC.B INCD.B INV.B JHS JEQ, JZ JGE Jump if less Hint JMPSUB R5,COUNT Count − R5 − Count JLO JNCJNZ JNEMOV.B MOV.WNOP POP.B PUSH.B PUSH.WRET Reti −13. Main Program InterruptRLA.B −14. Destination Operand-Arithmetic Shift LeftRLC.B −15. Destination Operand-Carry Left ShiftRRA.B RRA.WRRC.B RRC.WSBC.B Setc Setn Setz SUB.B SUB.WBorrow Implementation Swpb −18. Destination Operand Byte SwapSXT −19. Destination Operand Sign ExtensionTST.B XOR.B XOR.WFormat-III Jump Instruction Cycles and Lengths Interrupt and Reset CyclesInstruction Cycles and Lengths Format-II Single Operand Instruction Cycles and Lengths−16.Format 1 Instruction Cycles and Lengths Format-I Double Operand Instruction Cycles and Lengths−20. Core Instruction Map Instruction Set DescriptionMnemonic Description −17.MSP430 Instruction SetPage Chapter Basic Clock Module Introduction −1. Basic Clock Block Diagram Basic Clock Module Operation Basic Clock Module Features for Low-Power ApplicationsLFXT1 Oscillator −2. Off Signals for the LFXT1 Oscillator3 XT2 Oscillator Digitally-Controlled Oscillator DCODisabling the DCO −5. Typical DCOx Range and RSELx Steps Adjusting the DCO frequency−6. DCO Frequency vs. Temperature Using an External Resistor Rosc for the DCO−7. Modulator Patterns DCO ModulatorBasic Clock Module Fail-Safe Operation −9. Oscillator-Fault Signal−10. Oscillator-Fault-Interrupt Oscillator Fault DetectionSourcing Mclk from a Crystal −11. Switch Mclk from Dcoclk to LFXT1CLK Synchronization of Clock SignalsBasic Clock Module Registers −1. Basic Clock Module RegistersRegister Short Form Register Type Address Initial State BCSCTL1, Basic Clock System Control Register DCOCTL, DCO Control RegisterDIVSx BCSCTL2, Basic Clock System Control RegisterSELMx DIVMxIFG1, Interrupt Flag Register IE1, Interrupt Enable Register18Basic Clock Module Chapter Flash Memory Introduction −1. Flash Memory Module Block Diagram−2. Flash Memory Segments, 4-KB Example Flash Memory SegmentationFlash Memory Timing Generator Flash Memory OperationErase Mode Erasing Flash Memory−1. Erase Modes −5. Erase Cycle from Within Flash Memory Initiating an Erase from Within Flash Memory−6. Erase Cycle from Within RAM Initiating an Erase from RAMByte/Word Write Write ModeWriting Flash Memory −2. Write Modes−8. Initiating a Byte/Word Write from Flash Initiating a Byte/Word Write from Within Flash Memory−9. Initiating a Byte/Word Write from RAM Initiating a Byte/Word Write from RAM−10. Block-Write Cycle Timing Block Write−11. Block Write Flow Block Write Flow and ExampleKHz Smclk 952 kHz Assumes Accvie = Nmiie = Ofie = Result Flash Memory Access During Write or Erase−3. Flash Access While Busy = FlashProgramming Flash Memory Devices Configuring and Accessing the Flash Memory ControllerStopping a Write or Erase Cycle Flash Memory Controller InterruptsProgramming Flash Memory via Jtag −12. User-Developed Programming Solution−4. Flash Memory Registers Flash Memory RegistersFCTL1, Flash Memory Control Register ReservedErase Cycle FNx FCTL2, Flash Memory Control RegisterFWKEYx FSSELxFCTL3, Flash Memory Control Register FCTL3 Rather than MOV.B or CLR.B instructions Flash Memory Controller SVS Introduction SVS Operation SVS Registers SVS Introduction −1. SVS Block Diagram Configuring the SVS SVS OperationSVS Comparator Operation Changing the VLDx Bits −2. Svson state When Changing VLDxSVS Operating Range −3. Operating Levels for SVS and Brownout/Reset CircuitSVSCTL, SVS Control Register Read/write 055h Reset with BORSVS Registers −1. SVS RegistersSupply Voltage Supervisor Chapter Hardware Multiplier Introduction −1. Hardware Multiplier Block DiagramOP1 Address Register Name Operation Hardware Multiplier OperationOperand Registers −1. OP1 addressesMacs Underflow and Overflow −2. Reshi Contents−3. Sumext Contents Result RegistersProcess results Software ExamplesIndirect Addressing of Reslo Using Interrupts−4. Hardware Multiplier Registers Hardware Multiplier RegistersHardware Multiplier DMA Introduction DMA Operation DMA Registers DMA Introduction −1. DMA Controller Block Diagram DMA Addressing Modes DMA OperationDMADTx Transfer Description Mode DMA Transfer Modes−1. DMA Transfer Modes Single Transfer −3. DMA Single Transfer State Diagram Block Transfers −4. DMA Block Transfer State Diagram Burst-Block Transfers −5. DMA Burst-Block Transfer State Diagram Halting Executing Instructions for DMA Transfers Initiating DMA TransfersEdge-Sensitive Triggers Level-Sensitive TriggersDMAxTSELx Operation −2. DMA Trigger OperationStopping DMA Transfers DMA Channel PrioritiesDMA Priority Transfer Occurs New DMA Priority CPU Operating Mode Clock Source Maximum DMA Cycle Time DMA Transfer Cycle Time−3. Maximum Single-Transfer DMA Cycle Time DMA Controller Interrupts Using DMA with System InterruptsUsing the I2C Module with the DMA Controller Using ADC12 with the DMA ControllerUsing DAC12 With the DMA Controller −4. DMA Registers DMA RegistersTSELx DMACTL0, DMA Control RegisterDMACTL1, DMA Control Register Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMAxCTL, DMA Channel x Control RegisterDMAxSAx DMAxSA, DMA Source Address RegisterDMAxSZ, DMA Size Address Register DMAxDA, DMA Destination Address RegisterPage Chapter Digital I/O Introduction Direction Registers PxDIR Digital I/O OperationInput Register PxIN Output Registers PxOUTFunction Select Registers PxSEL Interrupt Flag Registers P1IFG, P2IFG 5 P1 and P2 InterruptsInterrupt Enable P1IE, P2IE Configuring Unused Port PinsInterrupt Edge Select Registers P1IES, P2IES −1. Digital I/O Registers Digital I/O RegistersDigital I/O Watchdog Timer Introduction 10-2 Watchdog Timer Operation 10-4Watchdog Timer Registers 10-7 Watchdog Timer Introduction −1. Watchdog Timer Block Diagram Interval Timer Mode Watchdog Timer OperationWatchdog Timer Counter Watchdog ModeWatchdog Timer Interrupts Software Examples Operation in Low-Power Modes−1.Watchdog Timer Registers Watchdog Timer RegistersWDTISx WDTCTL, Watchdog Timer RegisterNmiie Nmiifg TimerA Introduction 11-2 TimerA Operation 11-4TimerA Registers 11-19 TimerA Introduction −1. TimerA Block Diagram TimerA Operation 11.2.1 16-Bit Timer CounterClock Source Select and Divider MCx Mode Description Starting the TimerTimer Mode Control −1. Timer Modes−2. Up Mode Up Mode−4. Continuous Mode Continuous Mode−6. Continuous Mode Time Intervals Use of the Continuous Mode−7. Up/Down Mode Up/Down Mode−9. Output Unit in Up/Down Mode Use of the Up/Down ModeCapture/Compare Blocks Capture Mode−11. Capture Cycle Compare Mode−2. Output Modes OUTMODx Mode DescriptionOutput Unit Output Modes−12.Output Example-Timer in Up Mode −13.Output Example-Timer in Continuous Mode −14.Output Example-Timer in Up/Down Mode TimerA Interrupts TACCR0 InterruptTAIV, Interrupt Vector Generator Taiv Software Example −3. TimerA Registers TimerA RegistersIDx TACTL, TimerA Control RegisterUnused TASSELxTARx TAR, TimerA RegisterOUTMODx TACCTLx, Capture/Compare Control RegisterCMx CCISxInterrupt TAIV, TimerA Interrupt Vector RegisterTaiv Contents Interrupt Source Interrupt Flag Priority TAIVx11-24TimerA TimerB Introduction 12-2 TimerB Operation 12-4TimerB Registers 12-20 Similarities and Differences From TimerA TimerB Introduction−1. TimerB Block Diagram TimerB Operation 12.2.1 16-Bit Timer CounterTBR Length −1.Timer Modes Starting the TimerChanging the Period Register TBCL0 Way as the other capture/compare registers 12-8TimerB TBCL0−1 TBCL0 TBCL0−1 TBCL0−2 Changing the Value of Period Register TBCL0 −10. Capture Signal SCS=1 −11.Capture Cycle CLLDx Description TBCLGRPx Grouping Update Control−2.TBCLx Load Events −3.Compare Latch Operating Modes−4.Output Modes Output Unit−12. Output Example-Timer in Up Mode −13. Output Example-Timer in Continuous Mode −14. Output Example-Timer in Up/Down Mode TBIV, Interrupt Vector Generator TimerB InterruptsTBIV, Interrupt Handler Examples −5.TimerB Registers TimerB RegistersTimerB Control Register Tbctl CNTLxTBSSELx TBRx TBR, TimerB RegisterCLLDx TBCCTLx, Capture/Compare Control Register12-24TimerB TBIV, TimerB Interrupt Vector Register Tbiv Contents Interrupt Source Interrupt Flag PriorityTBIVx 12-26TimerB Usart Introduction Uart Mode 13-2 Usart Operation Uart Mode 13-4Usart Registers Uart Mode 13-21 −1 shows the Usart when configured for Uart mode Usart Introduction Uart Mode−1. Usart Block Diagram Uart Mode Usart Operation Uart Mode Usart Initialization and ResetCharacter Format Idle-Line Multiprocessor Format Asynchronous Communication Formats13-6USART Peripheral Interface, Uart Mode −4. Address -Bit Multiprocessor Format Address-Bit Multiprocessor FormatAutomatic Error Detection −1.Receive Error ConditionsError Condition Description −5. State Diagram of Receiver Enable Usart Receive Enable−6. State Diagram of Transmitter Enable Usart Transmit Enable−7. MSP430 Baud Rate Generator Uart Baud Rate GenerationDetermining the Modulation Value Baud Rate Bit TimingBrclk = Transmit Bit TimingReceive Bit Timing −9. Receive ErrorBrclk −2.Commonly Used Baud Rates, Baud Rate Data, and Errors Typical Baud Rates and ErrorsUsart Transmit Interrupt Operation Usart Interrupts−11.Receive Interrupt Operation Usart Receive Interrupt OperationReceive-Start Edge Detect Operation −12. Glitch Suppression, Usart Receive Not Started Usart Registers Uart Mode −3.USART0 Control and Status Registers−4.USART1 Control and Status Registers UxCTL, Usart Control Register SSELx UxTCTL, Usart Transmit Control RegisterUxRCTL, Usart Receive Control Register UxMCTL, Usart Modulation Control Register UxBRxUxMCTLx UxTXBUFx Bits UxRXBUF, Usart Receive Buffer RegisterUxTXBUF, Usart Transmit Buffer Register UxRXBUFx BitsME2, Module Enable Register ME1, Module Enable RegisterIE2, Interrupt Enable Register IE1, Interrupt Enable RegisterIFG2, Interrupt Flag Register IFG1, Interrupt Flag RegisterUTXIFG0 ‡ Usart Peripheral Interface, Uart Mode 13-31 Usart Introduction SPI Mode 14-2 Usart Operation SPI Mode 14-4Usart Registers SPI Mode 14-13 Usart Introduction SPI Mode −1. Usart Block Diagram SPI Mode Simo Usart Operation SPI ModeFour-Pin SPI Master Mode Master ModeFour-Pin SPI Slave Mode Slave ModeTransmit Enable SPI Enable−6. SPI Master Receive-Enable State Diagram Receive Enable−8. SPI Baud Rate Generator Serial Clock Control−9. Usart SPI Timing Serial Clock Polarity and PhaseSPI Transmit Interrupt Operation SPI InterruptsSPI Receive Interrupt Operation −12. Receive Interrupt State DiagramUsart Registers SPI Mode −1.USART0 Control and Status Registers−2.USART1 Control and Status Registers I2C † UxCTL, Usart Control RegisterCkph Undefined UxRCTL, Usart Receive Control RegisterBaud-rate generator uses the content of UxBR1+UxBR0 to set MSB is always reset USPIE0 † 14-20USART Peripheral Interface, SPI Mode USART0 14-22USART Peripheral Interface, SPI Mode Usart Peripheral Interface, SPI Mode 14-23 2C Module Introduction 15-2 2C Module Operation 15-42C Module Registers 15-20 START/RESTART/STOP 15.1 I2C Module Introduction−1. Usart Block Diagram I 2C Mode 15.2 I2C Module Operation −2. I 2C Bus Connection Diagram15.2.1 I2C Module Initialization −3. I 2C Module Data Transfer 15.2.2 I2C Serial Data15.2.3 I2C Addressing Modes Bit AddressingRepeated Start Conditions 15.2.4 I2C Module Operating Modes −1.Master OperationCondition Or Bus Activity −8. Master Transmitter Mode −9. Master Receiver Mode −10. Arbitration Procedure Between Two Master Transmitters Automatic Data Byte Counting −11.Slave Transmitter −12. Slave Receiver Receive Overrun I2C Data Register I2CDR−2.I2CDR Register Function Transmit Underflow−13. I 2C Module SCL Generation 15.2.6 I2C Clock Generation and SynchronizationUsing the I2C Module with Low Power Modes 15.2.8 I2C Interrupts −3.I 2C InterruptsInterrupt Interrupt Condition Flag I2CIV Software Example I2CIV, Interrupt Vector Generator−4.I 2C Registers 15.3 I2C Module RegistersU0CTL, USART0 Control Register-I2C Mode I2CSSELx I2CTCTL, I2C Transmit Control RegisterUnused I2CDCTL, I2C Data Control RegisterI2CDRW, I2CDRB, I2C Data Register I2CNDAT, I2C Transfer Byte Count RegisterI2CNDATx Bits I2CPSCx I2CPSC, I2C Clock Prescaler RegisterI2CSCLLx Bits I2CSCLH, I2C Shift Clock High RegisterI2CSCLL, I2C Shift Clock Low Register I2CSCLHx BitsI2COA, I2C Own Address Register, 7-Bit Addressing Mode I2COA, I2C Own Address Register, 10-Bit Addressing ModeI2COAx I2CSA, I2C Slave Address Register, 7-Bit Addressing Mode I2CSA, I2C Slave Address Register, 10-Bit Addressing ModeI2CSAx I2CIE, I2C Interrupt Enable Register I2CIFG, I2C Interrupt Flag Register I2CIV, I2C Interrupt Vector Register I2CIVI2CIVx 15-32USART Peripheral Interface, I2C Mode ComparatorA Introduction 16-2 ComparatorA Operation 16-4ComparatorA Registers 16-9 ComparatorA Introduction −1. ComparatorA Block Diagram Input Analog Switches ComparatorA OperationComparator Voltage Reference Generator Output FilterComparatorA Interrupts ComparatorA, Port Disable Register CapdComparatorA Used to Measure Resistive Elements −5. Temperature Measurement System−6. Timing for Temperature Measurement Systems −1.ComparatorA Registers ComparatorA RegistersCACTL1, ComparatorA Control Register CAPD, ComparatorA, Port Disable Register CACTL2, ComparatorA, Control RegisterCAPDx 16-12ComparatorA ADC12 Introduction 17-2 ADC12 Operation 17-4ADC12 Registers 17-20 17.1 ADC12 Introduction −1. ADC12 Block Diagram 17.2 ADC12 Operation 17.2.1 12-Bit ADC CoreConversion Clock Selection Analog Port Selection 17.2.2 ADC12 Inputs and MultiplexerVoltage Reference Generator Auto Power-DownSample and Conversion Timing Extended Sample Mode−4. Pulse Sample Mode Pulse Sample Mode−5. Analog Input Equivalent Circuit Sample Timing Considerations17.2.7 ADC12 Conversion Modes −1.Conversion Mode SummaryCONSEQx Mode Operation Conversion Memory−6. Single-Channel, Single-Conversion Mode Single-Channel Single-Conversion Mode−7. Sequence-of-Channels Mode Sequence-of-Channels Mode−8. Repeat-Single-Channel Mode Repeat-Single-Channel Mode−9. Repeat-Sequence-of-Channels Mode Repeat-Sequence-of-Channels ModeStopping Conversions Using the Multiple Sample and Convert MSC Bit−10. Typical Temperature Sensor Transfer Function Using the Integrated Temperature Sensor−11.ADC12 Grounding and Noise Considerations 17.2.9 ADC12 Grounding and Noise ConsiderationsADC12IV, Interrupt Vector Generator 17.2.10 ADC12 InterruptsADC12IFG15 ADC12 Interrupt Handling Software Example−2.ADC12 Registers 17.3 ADC12 RegistersADC12CTL0, ADC12 Control Register SHT1xSHT0x Bit Reference generator voltage. Refon must also be set ADC12DIVx ADC12CTL1, ADC12 Control RegisterADDx SHSxResults ADC12MEMx, ADC12 Conversion Memory RegistersCONSEQx ConversionADC12MCTLx, ADC12 Conversion Memory Control Registers SREFxINCHx ADC12IFGx Bits ADC12IE, ADC12 Interrupt Enable RegisterADC12IFG, ADC12 Interrupt Flag Register ADC12IExContents Interrupt Source Interrupt Flag Priority ADC12IV, ADC12 Interrupt Vector RegisterADC12IVx Bits 17-28 ADC12 ADC10 Introduction 18-2 ADC10 Operation 18-4ADC10 Registers 18-24 18.1 ADC10 Introduction −1. ADC10 Block Diagram 18.2.1 10-Bit ADC Core 18.2 ADC10 OperationAnalog Port Selection 18.2.2 ADC10 Inputs and MultiplexerVoltage Reference Generator Internal Reference Low-Power Features−3. Sample Timing −4. Analog Input Equivalent Circuit Conversion Modes −1.Conversion Mode Summary−5. Single-Channel Single-Conversion Mode −6. Sequence-of-Channels Mode −7. Repeat-Single-Channel Mode −8. Repeat-Sequence-of-Channels Mode Stopping Conversions Using the MSC Bit18.2.7 ADC10 Data Transfer Controller −9. One-Block Transfer One-Block Transfer Mode=0 ADC10DTC1 DTC reset Wait for write to −11.Two-Block Transfer Two-Block Transfer ModeADC10CT=1 −2.Maximum DTC Cycle Time CPU Operating Mode Clock Source Maximum DTC Cycle TimeContinuous Transfer DTC Transfer Cycle Time−14. Typical Temperature Sensor Transfer Function −16. ADC10 Grounding and Noise Considerations 18.2.9 ADC10 Grounding and Noise Considerations−17. ADC10 Interrupt System 18.2.10 ADC10 Interrupts−3.ADC10 Registers 18.3 ADC10 RegistersSHTx ADC10CTL0, ADC10 Control RegisterBit Reference-generator voltage. Refon must also be set INCHx ADC10CTL1, ADC10 Control RegisterADC10AE, Analog Input Enable Control Register ADC10DIVxADC10AEx Bits ADC10MEM, Conversion-Memory Register, 2’s Complement Format ADC10MEM, Conversion-Memory Register, Binary FormatReserved ADC10DTC0, Data Transfer Control RegisterADC10SAx ADC10DTC1, Data Transfer Control RegisterADC10SA, Start Address Register for Data Transfer Transfers18-32 ADC10 DAC12 Introduction 19-2 DAC12 Operation 19-4DAC12 Registers 19-10 19.1 DAC12 Introduction −1. DAC12 Block Diagram DAC12 Port Selection 19.2 DAC12 Operation19.2.1 DAC12 Core −1.DAC12 Full-Scale Range Vref = V eREF+ or VREF+19.2.2 DAC12 Reference DAC12 Reference Input and Voltage Output BuffersUpdating the DAC12 Voltage Output 19.2.4 DAC12xDAT Data Format −4. Negative Offset 19.2.5 DAC12 Output Amplifier Offset CalibrationGrouping Multiple DAC12 Modules −6. DAC12 Group Update Example, TimerA3 Trigger19.2.7 DAC12 Interrupts −2.DAC12 Registers 19.3 DAC12 RegistersLSELx DAC12xCTL, DAC12 Control RegisterAMPx DAC12AMPx Input Buffer Output BufferDAC12xDAT, DAC12 Data Register DAC12 DataDAC12 Data Format 19-14 DAC12