Texas Instruments MSP430x1xx manual TimerB Introduction, Similarities and Differences From TimerA

Timer_B Introduction

12.1 Timer_B Introduction

Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer_B features include :

-Asynchronous 16-bit timer/counter with four operating modes and four selectable lengths

-Selectable and configurable clock source

-Three or seven configurable capture/compare registers

-Configurable outputs with PWM capability

-Double-buffered compare latches with synchronized loading

-Interrupt vector register for fast decoding of all Timer_B interrupts

The block diagram of Timer_B is shown in Figure 12−1.

Note: Use of the Word Count

Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action does not take place.

12.1.1 Similarities and Differences From Timer_A

Timer_B is identical to Timer_A with the following exceptions:

-The length of Timer_B is programmable to be 8, 10, 12, or 16 bits.

-Timer_B TBCCRx registers are double-buffered and can be grouped.

-All Timer_B outputs can be put into a high-impedance state.

-The SCCI bit function is not implemented in Timer_B.

12-2Timer_B