Texas Instruments MSP430x1xx manual Transmit Bit Timing, Brclk =

USART Operation: UART Mode

Transmit Bit Timing

The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced. The individual bit error can be calculated by:

	￿		￿(j ) 1)	j	￿
Error [%] +		baud rate		UxBR ) S mi￿* (j ) 1)		100%
		BRCLK		i+0

With:

baud rate: Desired baud rate

BRCLK: Input frequency − UCLKI, ACLK, or SMCLK

j:Bit position - 0 for the start bit, 1 for data bit D0, and so on UxBR: Division factor in registers UxBR1 and UxBR0

For example, the transmit errors for the following conditions are calculated:

Baud rate =	2400
BRCLK =	32,768 Hz (ACLK)
UxBR =	13, since the ideal division factor is 13.65
UxMCTL =	6Bh: m7=0, m6=1, m5=1, m4=0, m3=1, m2=0,
	m1=1, and m0=1. The LSB of UxMCTL is used first.

Start bit Error [%] + ￿baud rate ((0 ) 1) UxBR ) 1)–1￿100% + 2.54%
BRCLK
Data bit D0 Error [%] + ￿baud rate	((1 ) 1)	UxBR ) 2)–2￿	100% + 5.08%
BRCLK
Data bit D1 Error [%] + ￿baud rate	((2 ) 1)	UxBR ) 2)–3￿	100% + 0.29%
BRCLK
Data bit D2 Error [%] + ￿baud rate	((3 ) 1)	UxBR ) 3)–4￿	100% + 2.83%
BRCLK
Data bit D3 Error [%] + ￿baud rate	((4 ) 1)	UxBR ) 3)–5￿	100% +*1.95%
BRCLK
Data bit D4 Error [%] + ￿baud rate	((5 ) 1)	UxBR ) 4)–6￿	100% + 0.59%
BRCLK
Data bit D5 Error [%] + ￿baud rate	((6 ) 1)	UxBR ) 5)–7￿	100% + 3.13%
BRCLK
Data bit D6 Error [%] + ￿baud rate	((7 ) 1)	UxBR ) 5)–8￿	100% + *1.66%
BRCLK
Data bit D7 Error [%] + ￿baud rate	((8 ) 1)	UxBR ) 6)–9￿	100% + 0.88%
BRCLK
Parity bit Error [%] + ￿baud rate	((9 ) 1)	UxBR ) 7)–10￿	100% + 3.42%
BRCLK
Stop bit 1 Error [%] + ￿baud rate	((10 ) 1)	UxBR ) 7)–11￿	100% + *1.37%
BRCLK

The results show the maximum per-bit error to be 5.08% of a BITCLK period.

USART Peripheral Interface, UART Mode 13-13