Texas Instruments MSP430x1xx manual UxRCTL, Usart Receive Control Register

USART Registers: UART Mode

UxRCTL, USART Receive Control Register

7 6 5 4

3 2 1 0

FE

PE

OE

BRK

URXEIE

URXWIE

RXWAKE

RXERR

rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0

FE	Bit 7	Framing error flag
		0	No error
		1	Character received with low stop bit
PE	Bit 6	Parity error flag. When PENA = 0, PE is read as 0.
		0	No error
		1	Character received with parity error
OE	Bit 5	Overrun error flag. This bit is set when a character is transferred into
		UxRXBUF before the previous character was read.
		0	No error
		1	Overrun error occurred
BRK	Bit 4	Break detect flag
		0	No break condition
		1	Break condition occurred
URXEIE	Bit 3	Receive erroneous-character interrupt-enable
		0	Erroneous characters rejected and URXIFGx is not set
		1	Erroneous characters received will set URXIFGx
URXWIE	Bit 2	Receive wake-up interrupt-enable. This bit enables URXIFGx to be set
		when an address character is received. When URXEIE = 0, an address
		character will not set URXIFGx if it is received with errors.
		0	All received characters set URXIFGx
		1	Only received address characters set URXIFGx
RXWAKE	Bit 1	Receive wake-up flag
		0	Received character is data
		1	Received character is an address
RXERR	Bit 0	Receive error flag. This bit indicates a character was received with error(s).
		When RXERR = 1, on or more error flags (FE,PE,OE, BRK) is also set.
		RXERR is cleared when UxRXBUF is read.
		0	No receive errors detected
		1	Receive error detected

13-24USART Peripheral Interface, UART Mode