Texas Instruments MSP430x1xx manual Stopping DMA Transfers, DMA Channel Priorities

8.2.4Stopping DMA Transfers

There are two ways to stop DMA transfers in progress:

-A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1.

-A burst-block transfer may be stopped by clearing the DMAEN bit.

8.2.5DMA Channel Priorities

The default DMA channel priorities are DMA0−DMA1−DMA2. If two or three triggers happen simultaneously or are pending, the channel with the highest priority completes its transfer (single, block or burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in progress are not halted if a higher priority channel is triggered. The higher priority channel waits until the transfer in progress completes before starting.

The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the channels always stays the same, DMA0−DMA1−DMA2, for example:

DMA Priority	Transfer Occurs	New DMA Priority
DMA0 − DMA1 − DMA2	DMA1	DMA2 − DMA0 − DMA1
DMA2 − DMA0 − DMA1	DMA2	DMA0 − DMA1 − DMA2
DMA0 − DMA1 − DMA2	DMA0	DMA1 − DMA2 − DMA0

When the ROUNDROBIN bit is cleared the channel priority returns to the default priority.

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