Texas Instruments MSP430x1xx manual Single-Operand Format II Instructions

Instruction Set

3.4.2Single-Operand (Format II) Instructions

Figure 3−10 illustrates the single-operand instruction format.

Figure 3−10. Single Operand Instruction Format

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				Op-code					B/W		Ad		D/S-Reg

Table 3−12 lists and describes the single operand instructions.

Table 3−12.Single Operand Instructions

Mnemonic	S-Reg,	Operation	Status Bits
	D-Reg		V	N	Z	C
RRC(.B)	dst	C → MSB →.......LSB → C	*	*	*	*
RRA(.B)	dst	MSB → MSB →....LSB → C	0	*	*	*
PUSH(.B)	src	SP − 2 → SP, src → @SP	−	−	−	−
SWPB	dst	Swap bytes	−	−	−	−
CALL	dst	SP − 2 → SP, PC+2 → @SP	−	−	−	−
		dst → PC
RETI		TOS → SR, SP + 2 → SP	*	*	*	*
		TOS → PC,SP + 2 → SP
SXT	dst	Bit 7 → Bit 8........Bit 15	0	*	*	*

*The status bit is affected

−The status bit is not affected 0 The status bit is cleared

1 The status bit is set

All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE) or the indexed mode x(RN) is used, the word that follows contains the address information.

RISC 16-Bit CPU 3-19