Texas Instruments MSP430x1xx ComparatorA, Port Disable Register Capd, ComparatorA Interrupts

Comparator_A Operation

16.2.5 Comparator_A, Port Disable Register CAPD

The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption.

The CAPDx bits, when set, disable the corresponding P2 input buffer as shown in Figure 16−3. When current consumption is crit ical, any P2 pin connected to analog signals should be disabled with their associated CAPDx bit.

Figure 16−3. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer

VCC

VI	VO
	ICC
VCC
CAPD.x = 1	VSS

ICC

VI

0VCC

16.2.6 Comparator_A Interrupts

One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 16−4. The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output, selected by the CAIES bit. If both the CAIE and the GIE bits are set, then the CAIFG flag generates an interrupt request. The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software.

Figure 16−4. Comparator_A Interrupt System

SET_CAIFG

	VCC
	CAIES
0	D	Q
1		Reset

CAIE

IRQ, Interrupt Service Requested

IRACC, Interrupt Request Accepted

POR

16-6Comparator_A