Texas Instruments MSP430x1xx manual Receive Bit Timing, 9. Receive Error

USART Operation: UART Mode

Receive Bit Timing

Receive timing consists of two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 13−9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock.

Figure 13−9. Receive Error

i

tideal

BRCLK

URXDx

URXDS

tactual

Sample

URXDS

						0								1									2
						t0									t1
1	2	3	4	5	6	7	8	9 10 11 12 13 14 1	2	3	4	5	6	7	8	9 10 11 12 13 14	1	2	3	4	5	6	7

		ST			D0		D1
		ST
					D0		D1
		t0			t1		t2
	Synchronization Error ± 0.5x BRCLK
Int(UxBR/2)+m0 =			UxBR +m1 = 13+1 = 14			UxBR +m2 = 13+0 = 13
Int (13/2)+1 = 6+1 = 7
	Majority Vote Taken			Majority Vote Taken			Majority Vote Taken

The ideal start bit timing tideal(0) is half the baud-rate timing tbaud rate because the bit is tested in the middle of its period. The ideal baud rate timing tideal(i) for the remaining character bits is the baud rate timing tbaud rate. The individual bit errors can be calculated by:

￿baud rate	￿	2	UxBR	￿￿)	￿	i	j	￿￿	* 1 * j	￿	100%
Error [%] +			￿m0 ) int ￿				UxBR ) S mi
￿ BRCLK			2				i+1
￿

Where:

baud rate is the required baud rate

BRCLK is the input frequency—selected for UCLK, ACLK, or SMCLK j = 0 for the start bit, 1 for data bit D0, and so on

UxBR is the division factor in registers UxBR1 and UxBR0

13-14USART Peripheral Interface, UART Mode