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Texas Instruments MSP430x1xx manual Flash Memory Access During Write or Erase, Result

Models: MSP430x1xx

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Flash Memory Operation

5.3.4Flash Memory Access During Write or Erase

When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable. Also if a write to flash is attempted with WRT=0, the ACCVIFG interrupt flag is set, and the flash memory is unaffected.

When a byte/word write or any erase operation is initiated from within flash memory, the flash controller returns op-code 03FFFh to the CPU at the next instruction fetch. Op-code 03FFFh is the JMP PC instruction. This causes the CPU to loop until the flash operation is finished. When the operation is finished and BUSY=0, the flash controller allows the CPU to fetch the proper op-code and program execution resumes.

The flash access conditions while BUSY=1 are listed in Table 5−3.

Table 5−3. Flash Access While BUSY = 1

Flash	Flash	WAIT	Result
Operation	Access

	Read	0	ACCVIFG = 0. 03FFFh is the value read
Any erase, or	Write	0	ACCVIFG = 1. Write is ignored
Byte/word write	Instruction	0	ACCVIFG = 0. CPU fetches 03FFFh. This
	Instruction	0	ACCVIFG = 0. CPU fetches 03FFFh. This
	fetch		is the JMP PC instruction.

	Any	0	ACCVIFG = 1, LOCK = 1
	Read	1	ACCVIFG = 0, 03FFFh is the value read
Block write	Write	1	ACCVIFG = 0, Write is ignored
	Instruction	1	ACCVIFG = 1, LOCK = 1
	fetch

All interrupt sources should be disabled before initiating any flash operation. If an enabled interrupt were to occur during a flash operation, the CPU would fetch 03FFFh as the address of the interrupt service routine. The CPU would then execute the JMP PC instruction while BUSY=1. When the flash operation finished, the CPU would begin executing code at address 03FFFh, not the correct address for interrupt service routine.

5-14	Flash Memory Controller

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Texas Instruments MSP430x1xx manual Flash Memory Access During Write or Erase, 3. Flash Access While Busy =, Result

Contents

User’s Guide Important Notice Products ApplicationsPreface Glossary Register Bit Accessibility and Initial Condition Register Bit ConventionsPage Introduction Risc 16-Bit CPU Basic Clock ModuleFlash Memory Controller Supply Voltage Supervisor Watchdog Timer TimerAUsart Peripheral Interface, SPI Mode 18 ADC10 Chapter Architecture Flexible Clock SystemEmbedded Emulation −1. MSP430 ArchitectureAddress Space Flash/ROM2 RAM Peripheral Modules Special Function Registers SFRsMemory Organization 6Introduction Chapter System Reset and Initialization −1. Power-On Reset and Power-Up Clear SchematicPower-On Reset POR −2. POR TimingBrownout Reset BOR −3. Brownout TimingDevice Initial Conditions After System Reset Software InitializationInterrupts −4. Interrupt PriorityReset/NMI Pin Non-Maskable Interrupts NMI−5. Block Diagram of Non-Maskable Interrupt Sources Flash Access Violation Oscillator FaultExample of an NMI Interrupt Handler Maskable InterruptsInterrupt Processing Interrupt AcceptanceReturn From Interrupt Interrupt NestingInterrupt Vectors −1. Interrupt Sources,Flags, and VectorsOperating Modes Mode CPU and Clocks Status −10. MSP430x1xx Operating Modes For Basic Clock SystemEntering and Exiting Low-Power Modes Extended Time in Low-Power ModesPrinciples for Low-Power Applications Connection of Unused Pins−2. Connection of Unused Pins 18System Resets, Interrupts, and Operating Modes Chapter CPU Introduction −1. CPU Block Diagram CPU Registers Program Counter PCStack Pointer SP −3. Stack PointerStatus Register SR −1. Description of Status Register BitsBit Description Constant Generator Registers CG1 and CG2 −2. Values of Constant Generators CG1, CG2Constant Generator − Expanded Instruction Set Register Constant RemarksGeneral−Purpose Registers R4 R15 −7. Register -Byte/Byte-Register OperationsAs/Ad Addressing Mode Syntax Description Addressing Modes−3. Source/Destination Operand Addressing Modes Register Mode −4. Register Mode DescriptionAssembler Code Content of ROM Indexed Mode −5. Indexed Mode DescriptionSymbolic Mode −6. Symbolic Mode DescriptionAbsolute Mode −7. Absolute Mode DescriptionIndirect Register Mode −8. Indirect Mode DescriptionIndirect Autoincrement Mode −9. Indirect Autoincrement Mode DescriptionImmediate Mode −10.Immediate Mode DescriptionInstruction Set Double-Operand Format I Instructions −11. Double Operand InstructionsMnemonic Reg Operation Status Bits Single-Operand Format II Instructions −12.Single Operand InstructionsJumps −13.Jump InstructionsMnemonic Reg, D-Reg Operation ADC.W ADC.BADD.W ADD.BADDC.W ADDC.BAND.W AND.BBIC.W BIC.BBIS.W BIS.BBIT.W BIT.BBR, Branch Call CLR.B Clrc Clrn Clrz CMP.W CMP.BDADC.B DADD.W DADD.B−12. Decrement Overlap DEC.BDECD.B Disable Interrupt DintEint IncdINC.B INCD.B INV.B JHS JEQ, JZ JGE Jump if less JMP HintSUB R5,COUNT Count − R5 − Count JNC JLOJNE JNZMOV.W MOV.BNOP POP.B PUSH.W PUSH.BRET −13. Main Program Interrupt Reti−14. Destination Operand-Arithmetic Shift Left RLA.B−15. Destination Operand-Carry Left Shift RLC.BRRA.W RRA.BRRC.W RRC.BSBC.B Setc Setn Setz SUB.W SUB.BBorrow Implementation −18. Destination Operand Byte Swap Swpb−19. Destination Operand Sign Extension SXTTST.B XOR.W XOR.BInterrupt and Reset Cycles Instruction Cycles and LengthsFormat-II Single Operand Instruction Cycles and Lengths Format-III Jump Instruction Cycles and LengthsFormat-I Double Operand Instruction Cycles and Lengths −16.Format 1 Instruction Cycles and LengthsInstruction Set Description −20. Core Instruction Map−17.MSP430 Instruction Set Mnemonic DescriptionPage Chapter Basic Clock Module Introduction −1. Basic Clock Block Diagram Basic Clock Module Features for Low-Power Applications Basic Clock Module Operation−2. Off Signals for the LFXT1 Oscillator LFXT1 Oscillator3 XT2 Oscillator Digitally-Controlled Oscillator DCODisabling the DCO Adjusting the DCO frequency −5. Typical DCOx Range and RSELx StepsUsing an External Resistor Rosc for the DCO −6. DCO Frequency vs. TemperatureDCO Modulator −7. Modulator Patterns−9. Oscillator-Fault Signal Basic Clock Module Fail-Safe OperationOscillator Fault Detection −10. Oscillator-Fault-InterruptSourcing Mclk from a Crystal Synchronization of Clock Signals −11. Switch Mclk from Dcoclk to LFXT1CLKBasic Clock Module Registers −1. Basic Clock Module RegistersRegister Short Form Register Type Address Initial State DCOCTL, DCO Control Register BCSCTL1, Basic Clock System Control RegisterBCSCTL2, Basic Clock System Control Register SELMxDIVMx DIVSxIE1, Interrupt Enable Register IFG1, Interrupt Flag Register18Basic Clock Module Chapter −1. Flash Memory Module Block Diagram Flash Memory IntroductionFlash Memory Segmentation −2. Flash Memory Segments, 4-KB ExampleFlash Memory Operation Flash Memory Timing GeneratorErase Mode Erasing Flash Memory−1. Erase Modes Initiating an Erase from Within Flash Memory −5. Erase Cycle from Within Flash MemoryInitiating an Erase from RAM −6. Erase Cycle from Within RAMWrite Mode Writing Flash Memory−2. Write Modes Byte/Word WriteInitiating a Byte/Word Write from Within Flash Memory −8. Initiating a Byte/Word Write from FlashInitiating a Byte/Word Write from RAM −9. Initiating a Byte/Word Write from RAMBlock Write −10. Block-Write Cycle TimingBlock Write Flow and Example −11. Block Write FlowKHz Smclk 952 kHz Assumes Accvie = Nmiie = Ofie = Flash Memory Access During Write or Erase −3. Flash Access While Busy =Flash ResultConfiguring and Accessing the Flash Memory Controller Stopping a Write or Erase CycleFlash Memory Controller Interrupts Programming Flash Memory Devices−12. User-Developed Programming Solution Programming Flash Memory via JtagFlash Memory Registers −4. Flash Memory RegistersFCTL1, Flash Memory Control Register ReservedErase Cycle FCTL2, Flash Memory Control Register FWKEYxFSSELx FNxFCTL3, Flash Memory Control Register FCTL3 Rather than MOV.B or CLR.B instructions Flash Memory Controller SVS Introduction SVS Operation SVS Registers SVS Introduction −1. SVS Block Diagram Configuring the SVS SVS OperationSVS Comparator Operation −2. Svson state When Changing VLDx Changing the VLDx Bits−3. Operating Levels for SVS and Brownout/Reset Circuit SVS Operating RangeRead/write 055h Reset with BOR SVS Registers−1. SVS Registers SVSCTL, SVS Control RegisterSupply Voltage Supervisor Chapter −1. Hardware Multiplier Block Diagram Hardware Multiplier IntroductionHardware Multiplier Operation Operand Registers−1. OP1 addresses OP1 Address Register Name Operation−2. Reshi Contents −3. Sumext ContentsResult Registers Macs Underflow and OverflowSoftware Examples Process resultsUsing Interrupts Indirect Addressing of ResloHardware Multiplier Registers −4. Hardware Multiplier RegistersHardware Multiplier DMA Introduction DMA Operation DMA Registers DMA Introduction −1. DMA Controller Block Diagram DMA Operation DMA Addressing ModesDMADTx Transfer Description Mode DMA Transfer Modes−1. DMA Transfer Modes Single Transfer −3. DMA Single Transfer State Diagram Block Transfers −4. DMA Block Transfer State Diagram Burst-Block Transfers −5. DMA Burst-Block Transfer State Diagram Initiating DMA Transfers Edge-Sensitive TriggersLevel-Sensitive Triggers Halting Executing Instructions for DMA Transfers−2. DMA Trigger Operation DMAxTSELx OperationStopping DMA Transfers DMA Channel PrioritiesDMA Priority Transfer Occurs New DMA Priority CPU Operating Mode Clock Source Maximum DMA Cycle Time DMA Transfer Cycle Time−3. Maximum Single-Transfer DMA Cycle Time Using DMA with System Interrupts DMA Controller InterruptsUsing the I2C Module with the DMA Controller Using ADC12 with the DMA ControllerUsing DAC12 With the DMA Controller DMA Registers −4. DMA RegistersDMACTL0, DMA Control Register TSELxDMACTL1, DMA Control Register DMAxCTL, DMA Channel x Control Register Reserved DMADTx DMA DSTINCRx DMA SRCINCRxDMAxSA, DMA Source Address Register DMAxSAxDMAxDA, DMA Destination Address Register DMAxSZ, DMA Size Address RegisterPage Chapter Digital I/O Introduction Digital I/O Operation Input Register PxINOutput Registers PxOUT Direction Registers PxDIRFunction Select Registers PxSEL 5 P1 and P2 Interrupts Interrupt Flag Registers P1IFG, P2IFGInterrupt Enable P1IE, P2IE Configuring Unused Port PinsInterrupt Edge Select Registers P1IES, P2IES Digital I/O Registers −1. Digital I/O RegistersDigital I/O Watchdog Timer Introduction 10-2 Watchdog Timer Operation 10-4Watchdog Timer Registers 10-7 Watchdog Timer Introduction −1. Watchdog Timer Block Diagram Watchdog Timer Operation Watchdog Timer CounterWatchdog Mode Interval Timer ModeWatchdog Timer Interrupts Operation in Low-Power Modes Software ExamplesWatchdog Timer Registers −1.Watchdog Timer RegistersWDTCTL, Watchdog Timer Register WDTISxNmiie Nmiifg TimerA Introduction 11-2 TimerA Operation 11-4TimerA Registers 11-19 TimerA Introduction −1. TimerA Block Diagram TimerA Operation 11.2.1 16-Bit Timer CounterClock Source Select and Divider Starting the Timer Timer Mode Control−1. Timer Modes MCx Mode DescriptionUp Mode −2. Up ModeContinuous Mode −4. Continuous ModeUse of the Continuous Mode −6. Continuous Mode Time IntervalsUp/Down Mode −7. Up/Down ModeUse of the Up/Down Mode −9. Output Unit in Up/Down ModeCapture Mode Capture/Compare BlocksCompare Mode −11. Capture CycleOUTMODx Mode Description Output UnitOutput Modes −2. Output Modes−12.Output Example-Timer in Up Mode −13.Output Example-Timer in Continuous Mode −14.Output Example-Timer in Up/Down Mode TimerA Interrupts TACCR0 InterruptTAIV, Interrupt Vector Generator Taiv Software Example TimerA Registers −3. TimerA RegistersTACTL, TimerA Control Register UnusedTASSELx IDxTAR, TimerA Register TARxTACCTLx, Capture/Compare Control Register CMxCCISx OUTMODxTAIV, TimerA Interrupt Vector Register Taiv Contents Interrupt Source Interrupt Flag PriorityTAIVx Interrupt11-24TimerA TimerB Introduction 12-2 TimerB Operation 12-4TimerB Registers 12-20 TimerB Introduction Similarities and Differences From TimerA−1. TimerB Block Diagram TimerB Operation 12.2.1 16-Bit Timer CounterTBR Length Starting the Timer −1.Timer ModesChanging the Period Register TBCL0 Way as the other capture/compare registers 12-8TimerB TBCL0−1 TBCL0 TBCL0−1 TBCL0−2 Changing the Value of Period Register TBCL0 −10. Capture Signal SCS=1 −11.Capture Cycle TBCLGRPx Grouping Update Control −2.TBCLx Load Events−3.Compare Latch Operating Modes CLLDx DescriptionOutput Unit −4.Output Modes−12. Output Example-Timer in Up Mode −13. Output Example-Timer in Continuous Mode −14. Output Example-Timer in Up/Down Mode TimerB Interrupts TBIV, Interrupt Vector GeneratorTBIV, Interrupt Handler Examples TimerB Registers −5.TimerB RegistersTimerB Control Register Tbctl CNTLxTBSSELx TBR, TimerB Register TBRxTBCCTLx, Capture/Compare Control Register CLLDx12-24TimerB TBIV, TimerB Interrupt Vector Register Tbiv Contents Interrupt Source Interrupt Flag PriorityTBIVx 12-26TimerB Usart Introduction Uart Mode 13-2 Usart Operation Uart Mode 13-4Usart Registers Uart Mode 13-21 Usart Introduction Uart Mode −1 shows the Usart when configured for Uart mode−1. Usart Block Diagram Uart Mode Usart Operation Uart Mode Usart Initialization and ResetCharacter Format Asynchronous Communication Formats Idle-Line Multiprocessor Format13-6USART Peripheral Interface, Uart Mode Address-Bit Multiprocessor Format −4. Address -Bit Multiprocessor FormatAutomatic Error Detection −1.Receive Error ConditionsError Condition Description Usart Receive Enable −5. State Diagram of Receiver EnableUsart Transmit Enable −6. State Diagram of Transmitter EnableUart Baud Rate Generation −7. MSP430 Baud Rate GeneratorBaud Rate Bit Timing Determining the Modulation ValueTransmit Bit Timing Brclk =−9. Receive Error Receive Bit TimingBrclk Typical Baud Rates and Errors −2.Commonly Used Baud Rates, Baud Rate Data, and ErrorsUsart Interrupts Usart Transmit Interrupt OperationUsart Receive Interrupt Operation −11.Receive Interrupt OperationReceive-Start Edge Detect Operation −12. Glitch Suppression, Usart Receive Not Started Usart Registers Uart Mode −3.USART0 Control and Status Registers−4.USART1 Control and Status Registers UxCTL, Usart Control Register UxTCTL, Usart Transmit Control Register SSELxUxRCTL, Usart Receive Control Register UxMCTL, Usart Modulation Control Register UxBRxUxMCTLx UxRXBUF, Usart Receive Buffer Register UxTXBUF, Usart Transmit Buffer RegisterUxRXBUFx Bits UxTXBUFx BitsME1, Module Enable Register ME2, Module Enable RegisterIE1, Interrupt Enable Register IE2, Interrupt Enable RegisterIFG1, Interrupt Flag Register IFG2, Interrupt Flag RegisterUTXIFG0 ‡ Usart Peripheral Interface, Uart Mode 13-31 Usart Introduction SPI Mode 14-2 Usart Operation SPI Mode 14-4Usart Registers SPI Mode 14-13 Usart Introduction SPI Mode −1. Usart Block Diagram SPI Mode Usart Operation SPI Mode SimoMaster Mode Four-Pin SPI Master ModeSlave Mode Four-Pin SPI Slave ModeSPI Enable Transmit EnableReceive Enable −6. SPI Master Receive-Enable State DiagramSerial Clock Control −8. SPI Baud Rate GeneratorSerial Clock Polarity and Phase −9. Usart SPI TimingSPI Interrupts SPI Transmit Interrupt Operation−12. Receive Interrupt State Diagram SPI Receive Interrupt OperationUsart Registers SPI Mode −1.USART0 Control and Status Registers−2.USART1 Control and Status Registers UxCTL, Usart Control Register I2C †Ckph UxRCTL, Usart Receive Control Register UndefinedBaud-rate generator uses the content of UxBR1+UxBR0 to set MSB is always reset USPIE0 † 14-20USART Peripheral Interface, SPI Mode USART0 14-22USART Peripheral Interface, SPI Mode Usart Peripheral Interface, SPI Mode 14-23 2C Module Introduction 15-2 2C Module Operation 15-42C Module Registers 15-20 15.1 I2C Module Introduction START/RESTART/STOP−1. Usart Block Diagram I 2C Mode −2. I 2C Bus Connection Diagram 15.2 I2C Module Operation15.2.1 I2C Module Initialization 15.2.2 I2C Serial Data −3. I 2C Module Data Transfer15.2.3 I2C Addressing Modes Bit AddressingRepeated Start Conditions 15.2.4 I2C Module Operating Modes −1.Master OperationCondition Or Bus Activity −8. Master Transmitter Mode −9. Master Receiver Mode −10. Arbitration Procedure Between Two Master Transmitters Automatic Data Byte Counting −11.Slave Transmitter −12. Slave Receiver I2C Data Register I2CDR −2.I2CDR Register FunctionTransmit Underflow Receive Overrun15.2.6 I2C Clock Generation and Synchronization −13. I 2C Module SCL GenerationUsing the I2C Module with Low Power Modes 15.2.8 I2C Interrupts −3.I 2C InterruptsInterrupt Interrupt Condition Flag I2CIV, Interrupt Vector Generator I2CIV Software Example15.3 I2C Module Registers −4.I 2C RegistersU0CTL, USART0 Control Register-I2C Mode I2CTCTL, I2C Transmit Control Register I2CSSELxI2CDCTL, I2C Data Control Register UnusedI2CDRW, I2CDRB, I2C Data Register I2CNDAT, I2C Transfer Byte Count RegisterI2CNDATx Bits I2CPSC, I2C Clock Prescaler Register I2CPSCxI2CSCLH, I2C Shift Clock High Register I2CSCLL, I2C Shift Clock Low RegisterI2CSCLHx Bits I2CSCLLx BitsI2COA, I2C Own Address Register, 7-Bit Addressing Mode I2COA, I2C Own Address Register, 10-Bit Addressing ModeI2COAx I2CSA, I2C Slave Address Register, 7-Bit Addressing Mode I2CSA, I2C Slave Address Register, 10-Bit Addressing ModeI2CSAx I2CIE, I2C Interrupt Enable Register I2CIFG, I2C Interrupt Flag Register I2CIV, I2C Interrupt Vector Register I2CIVI2CIVx 15-32USART Peripheral Interface, I2C Mode ComparatorA Introduction 16-2 ComparatorA Operation 16-4ComparatorA Registers 16-9 ComparatorA Introduction −1. ComparatorA Block Diagram Input Analog Switches ComparatorA OperationComparator Output Filter Voltage Reference GeneratorComparatorA, Port Disable Register Capd ComparatorA Interrupts−5. Temperature Measurement System ComparatorA Used to Measure Resistive Elements−6. Timing for Temperature Measurement Systems ComparatorA Registers −1.ComparatorA RegistersCACTL1, ComparatorA Control Register CAPD, ComparatorA, Port Disable Register CACTL2, ComparatorA, Control RegisterCAPDx 16-12ComparatorA ADC12 Introduction 17-2 ADC12 Operation 17-4ADC12 Registers 17-20 17.1 ADC12 Introduction −1. ADC12 Block Diagram 17.2 ADC12 Operation 17.2.1 12-Bit ADC CoreConversion Clock Selection 17.2.2 ADC12 Inputs and Multiplexer Analog Port SelectionAuto Power-Down Voltage Reference GeneratorExtended Sample Mode Sample and Conversion TimingPulse Sample Mode −4. Pulse Sample ModeSample Timing Considerations −5. Analog Input Equivalent Circuit−1.Conversion Mode Summary CONSEQx Mode OperationConversion Memory 17.2.7 ADC12 Conversion ModesSingle-Channel Single-Conversion Mode −6. Single-Channel, Single-Conversion ModeSequence-of-Channels Mode −7. Sequence-of-Channels ModeRepeat-Single-Channel Mode −8. Repeat-Single-Channel ModeRepeat-Sequence-of-Channels Mode −9. Repeat-Sequence-of-Channels ModeUsing the Multiple Sample and Convert MSC Bit Stopping ConversionsUsing the Integrated Temperature Sensor −10. Typical Temperature Sensor Transfer Function17.2.9 ADC12 Grounding and Noise Considerations −11.ADC12 Grounding and Noise Considerations17.2.10 ADC12 Interrupts ADC12IV, Interrupt Vector GeneratorADC12 Interrupt Handling Software Example ADC12IFG1517.3 ADC12 Registers −2.ADC12 RegistersADC12CTL0, ADC12 Control Register SHT1xSHT0x Bit Reference generator voltage. Refon must also be set ADC12CTL1, ADC12 Control Register ADDxSHSx ADC12DIVxADC12MEMx, ADC12 Conversion Memory Registers CONSEQxConversion ResultsADC12MCTLx, ADC12 Conversion Memory Control Registers SREFxINCHx ADC12IE, ADC12 Interrupt Enable Register ADC12IFG, ADC12 Interrupt Flag RegisterADC12IEx ADC12IFGx BitsContents Interrupt Source Interrupt Flag Priority ADC12IV, ADC12 Interrupt Vector RegisterADC12IVx Bits 17-28 ADC12 ADC10 Introduction 18-2 ADC10 Operation 18-4ADC10 Registers 18-24 18.1 ADC10 Introduction −1. ADC10 Block Diagram 18.2 ADC10 Operation 18.2.1 10-Bit ADC Core18.2.2 ADC10 Inputs and Multiplexer Analog Port SelectionInternal Reference Low-Power Features Voltage Reference Generator−3. Sample Timing −4. Analog Input Equivalent Circuit −1.Conversion Mode Summary Conversion Modes−5. Single-Channel Single-Conversion Mode −6. Sequence-of-Channels Mode −7. Repeat-Single-Channel Mode −8. Repeat-Sequence-of-Channels Mode Using the MSC Bit Stopping Conversions18.2.7 ADC10 Data Transfer Controller One-Block Transfer Mode −9. One-Block Transfer=0 ADC10DTC1 DTC reset Wait for write to Two-Block Transfer Mode −11.Two-Block TransferADC10CT=1 CPU Operating Mode Clock Source Maximum DTC Cycle Time Continuous TransferDTC Transfer Cycle Time −2.Maximum DTC Cycle Time−14. Typical Temperature Sensor Transfer Function 18.2.9 ADC10 Grounding and Noise Considerations −16. ADC10 Grounding and Noise Considerations18.2.10 ADC10 Interrupts −17. ADC10 Interrupt System18.3 ADC10 Registers −3.ADC10 RegistersADC10CTL0, ADC10 Control Register SHTxBit Reference-generator voltage. Refon must also be set ADC10CTL1, ADC10 Control Register INCHxADC10AE, Analog Input Enable Control Register ADC10DIVxADC10AEx Bits ADC10MEM, Conversion-Memory Register, Binary Format ADC10MEM, Conversion-Memory Register, 2’s Complement FormatADC10DTC0, Data Transfer Control Register ReservedADC10DTC1, Data Transfer Control Register ADC10SA, Start Address Register for Data TransferTransfers ADC10SAx18-32 ADC10 DAC12 Introduction 19-2 DAC12 Operation 19-4DAC12 Registers 19-10 19.1 DAC12 Introduction −1. DAC12 Block Diagram 19.2 DAC12 Operation 19.2.1 DAC12 Core−1.DAC12 Full-Scale Range Vref = V eREF+ or VREF+ DAC12 Port Selection19.2.2 DAC12 Reference DAC12 Reference Input and Voltage Output BuffersUpdating the DAC12 Voltage Output 19.2.4 DAC12xDAT Data Format 19.2.5 DAC12 Output Amplifier Offset Calibration −4. Negative Offset−6. DAC12 Group Update Example, TimerA3 Trigger Grouping Multiple DAC12 Modules19.2.7 DAC12 Interrupts 19.3 DAC12 Registers −2.DAC12 RegistersDAC12xCTL, DAC12 Control Register LSELxDAC12AMPx Input Buffer Output Buffer AMPxDAC12xDAT, DAC12 Data Register DAC12 DataDAC12 Data Format 19-14 DAC12