I2C Module Operation

15.2.5 The I2C Data Register I2CDR

The I2CDR register can be accessed as an 8-bit or 16-bit register selected by the I2CWORD bit. The I2CDR register functions as described in Table 15−2. When I2CWORD = 1, any attempt to modify the register with a byte instruction will fail and the register will not be modified.

Table 15−2.I2CDR Register Function

I2CWORD I2CTRX

I2CDR Function

01 Byte mode transmit: Only the low byte is used. The byte is double buffered. If a new byte is written before the previous byte has been transmitted, the new byte is held in a temporary buffer before being latched into the I2CDR low byte. TXRDYIFG is set when I2CDR is ready to be accessed. I2CDR should be written after I2CSTT is set.

00 Byte mode receive: Only the low byte is used. The byte is double buffered. If a new byte is received before the previous byte has been read, the new byte is held in a temporary buffer before being latched into the I2CDR low byte. RXRDYIFG is set when I2CDR is ready to be read.

11 Word mode transmit: The low byte of the word is sent first, then the high byte. The register is double buffered. If a new word is written before the previous word has been transmitted, the new word is held in a temporary buffer before being latched into the I2CDR register. TXRDYIFG is set when I2CDR is ready to be accessed. I2CDR should be written after I2CSTT is set.

10 Word mode receive: The low byte of the word was received first, then the high byte. The register is double buffered. If a new word is received before the previous word has been read, the new word is held in a temporary buffer before being latched into the I2CDR register. RXRDYIFG is set when I2CDR is ready to be accessed.

Transmit Underflow

In master mode, underflow occurs when the transmit shift register and the transmit buffer are empty. In slave mode, underflow occurs when the transmit shift register and the transmit buffer are empty and the external I2C master still requests data. When transmit underflow occurs, the I2CTXUDF bit is set. Writing data to the I2CDR register or resetting the I2CEN bit resets I2CTXUDF. I2CTXUDF is used in transmit mode only.

Receive Overrun

Receive overrun occurs when the receive shift register is full and the receive buffer is full. The I2CRXOVR bit is set when receive overrun occurs. No data is lost because SCL is held low in this condition, which stops further bus activity. Reading the I2CDR register or resetting I2CEN resets I2CRXOVR. The I2CRXOVR bit is used in receive mode only.

USART Peripheral Interface, I2C Mode

15-15

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Texas Instruments MSP430x1xx manual I2C Data Register I2CDR, 2.I2CDR Register Function, Transmit Underflow, Receive Overrun

MSP430x1xx specifications

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