Texas Instruments MSP430x1xx manual TBIV, Interrupt Handler Examples

Timer_B Operation

TBIV, Interrupt Handler Examples

The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine.

The numbers at the right margin show the necessary CPU clock cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are:

- Capture/compare block CCR0	11 cycles
- Capture/compare blocks CCR1 to CCR6	16 cycles
- Timer overflow TBIFG	14 cycles

The following software example shows the recommended use of TBIV for Timer_B3.

; Interrupt handler for TBCCR0 CCIFG.				Cycles
CCIFG_0_HND
	...	; Start of handler Interrupt latency			6
	RETI				5
; Interrupt handler for TBIFG, TBCCR1 and TBCCR2 CCIFG.
TB_HND	...		; Interrupt latency		6
	ADD	&TBIV,PC	; Add offset to Jump table		3
	RETI		; Vector	0: No interrupt	5
	JMP	CCIFG_1_HND	; Vector	2: Module 1	2
	JMP	CCIFG_2_HND	; Vector	4: Module 2	2
	RETI		; Vector	6
	RETI		; Vector	8
	RETI		; Vector 10
	RETI		; Vector 12
TBIFG_HND			; Vector 14: TIMOV Flag
	...		; Task starts here
	RETI				5
CCIFG_2_HND			; Vector 4: Module 2
	...		; Task starts here
	RETI		; Back to main program		5

;The Module 1 handler shows a way to look if any other

;interrupt is pending: 5 cycles have to be spent, but

;9 cycles may be saved if another interrupt is pending

CCIFG_1_HND		; Vector 6: Module 3
...		;	Task	starts here
JMP	TB_HND	;	Look	for pending	ints	2

Timer_B 12-19