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Texas Instruments MSP430x1xx manual Format-I Double Operand Instruction Cycles and Lengths

Models: MSP430x1xx

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Instruction Set

Format-I (Double Operand) Instruction Cycles and Lengths

Table 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions.

Table 3−16.Format 1 Instruction Cycles and Lengths

Addressing Mode		No. of	Length of
Src	Dst	Cycles	Instruction		Example
Src	Dst				Example
Rn	Rm	1	1	MOV	R5,R8
	PC	2	1	BR	R9
	x(Rm)	4	2	ADD	R5,4(R6)
	EDE	4	2	XOR	R8,EDE
	&EDE	4	2	MOV	R5,&EDE

@Rn	Rm	2	1	AND	@R4,R5
	PC	2	1	BR	@R8
	x(Rm)	5	2	XOR	@R5,8(R6)
	EDE	5	2	MOV	@R5,EDE
	&EDE	5	2	XOR	@R5,&EDE

@Rn+	Rm	2	1	ADD	@R5+,R6
	PC	3	1	BR	@R9+
	x(Rm)	5	2	XOR	@R5,8(R6)
	EDE	5	2	MOV	@R9+,EDE
	&EDE	5	2	MOV	@R9+,&EDE

#N	Rm	2	2	MOV	#20,R9
	PC	3	2	BR	#2AEh
	x(Rm)	5	3	MOV	#0300h,0(SP)
	EDE	5	3	ADD	#33,EDE
	&EDE	5	3	ADD	#33,&EDE

x(Rn)	Rm	3	2	MOV	2(R5),R7
	PC	3	2	BR	2(R6)
	TONI	6	3	MOV	4(R7),TONI
	x(Rm)	6	3	ADD	4(R4),6(R9)
	&TONI	6	3	MOV	2(R4),&TONI

EDE	Rm	3	2	AND	EDE,R6
	PC	3	2	BR	EDE
	TONI	6	3	CMP	EDE,TONI
	x(Rm)	6	3	MOV	EDE,0(SP)
	&TONI	6	3	MOV	EDE,&TONI

&EDE	Rm	3	2	MOV	&EDE,R8
	PC	3	2	BRA	&EDE
	TONI	6	3	MOV	&EDE,TONI
	x(Rm)	6	3	MOV	&EDE,0(SP)
	&TONI	6	3	MOV	&EDE,&TONI

RISC 16−Bit CPU

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Texas Instruments MSP430x1xx manual Format-I Double Operand Instruction Cycles and Lengths

Contents

User’s Guide Products Applications Important NoticePreface Glossary Register Bit Conventions Register Bit Accessibility and Initial ConditionPage Introduction Basic Clock Module Risc 16-Bit CPUFlash Memory Controller Supply Voltage Supervisor TimerA Watchdog TimerUsart Peripheral Interface, SPI Mode 18 ADC10 Chapter Flexible Clock System Architecture−1. MSP430 Architecture Embedded EmulationFlash/ROM Address Space2 RAM Special Function Registers SFRs Peripheral ModulesMemory Organization 6Introduction Chapter −1. Power-On Reset and Power-Up Clear Schematic System Reset and Initialization−2. POR Timing Power-On Reset POR−3. Brownout Timing Brownout Reset BORSoftware Initialization Device Initial Conditions After System Reset−4. Interrupt Priority InterruptsNon-Maskable Interrupts NMI Reset/NMI Pin−5. Block Diagram of Non-Maskable Interrupt Sources Oscillator Fault Flash Access ViolationMaskable Interrupts Example of an NMI Interrupt HandlerInterrupt Acceptance Interrupt ProcessingInterrupt Nesting Return From Interrupt−1. Interrupt Sources,Flags, and Vectors Interrupt VectorsOperating Modes −10. MSP430x1xx Operating Modes For Basic Clock System Mode CPU and Clocks StatusExtended Time in Low-Power Modes Entering and Exiting Low-Power ModesConnection of Unused Pins Principles for Low-Power Applications−2. Connection of Unused Pins 18System Resets, Interrupts, and Operating Modes Chapter CPU Introduction −1. CPU Block Diagram Program Counter PC CPU Registers−3. Stack Pointer Stack Pointer SP−1. Description of Status Register Bits Status Register SRBit Description −2. Values of Constant Generators CG1, CG2 Constant Generator Registers CG1 and CG2Constant Generator − Expanded Instruction Set Register Constant Remarks−7. Register -Byte/Byte-Register Operations General−Purpose Registers R4 R15Addressing Modes As/Ad Addressing Mode Syntax Description−3. Source/Destination Operand Addressing Modes −4. Register Mode Description Register ModeAssembler Code Content of ROM −5. Indexed Mode Description Indexed Mode−6. Symbolic Mode Description Symbolic Mode−7. Absolute Mode Description Absolute Mode−8. Indirect Mode Description Indirect Register Mode−9. Indirect Autoincrement Mode Description Indirect Autoincrement Mode−10.Immediate Mode Description Immediate ModeInstruction Set −11. Double Operand Instructions Double-Operand Format I InstructionsMnemonic Reg Operation Status Bits −12.Single Operand Instructions Single-Operand Format II Instructions−13.Jump Instructions JumpsMnemonic Reg, D-Reg Operation ADC.B ADC.WADD.B ADD.WADDC.B ADDC.WAND.B AND.WBIC.B BIC.WBIS.B BIS.WBIT.B BIT.WBR, Branch Call CLR.B Clrc Clrn Clrz CMP.B CMP.WDADC.B DADD.B DADD.WDEC.B −12. Decrement OverlapDECD.B Dint Disable InterruptIncd EintINC.B INCD.B INV.B JHS JEQ, JZ JGE Jump if less Hint JMPSUB R5,COUNT Count − R5 − Count JLO JNCJNZ JNEMOV.B MOV.WNOP POP.B PUSH.B PUSH.WRET Reti −13. Main Program InterruptRLA.B −14. Destination Operand-Arithmetic Shift LeftRLC.B −15. Destination Operand-Carry Left ShiftRRA.B RRA.WRRC.B RRC.WSBC.B Setc Setn Setz SUB.B SUB.WBorrow Implementation Swpb −18. Destination Operand Byte SwapSXT −19. Destination Operand Sign ExtensionTST.B XOR.B XOR.WInstruction Cycles and Lengths Interrupt and Reset CyclesFormat-II Single Operand Instruction Cycles and Lengths Format-III Jump Instruction Cycles and Lengths−16.Format 1 Instruction Cycles and Lengths Format-I Double Operand Instruction Cycles and Lengths−20. Core Instruction Map Instruction Set DescriptionMnemonic Description −17.MSP430 Instruction SetPage Chapter Basic Clock Module Introduction −1. Basic Clock Block Diagram Basic Clock Module Operation Basic Clock Module Features for Low-Power ApplicationsLFXT1 Oscillator −2. Off Signals for the LFXT1 OscillatorDigitally-Controlled Oscillator DCO 3 XT2 OscillatorDisabling the DCO −5. Typical DCOx Range and RSELx Steps Adjusting the DCO frequency−6. DCO Frequency vs. Temperature Using an External Resistor Rosc for the DCO−7. Modulator Patterns DCO ModulatorBasic Clock Module Fail-Safe Operation −9. Oscillator-Fault Signal−10. Oscillator-Fault-Interrupt Oscillator Fault DetectionSourcing Mclk from a Crystal −11. Switch Mclk from Dcoclk to LFXT1CLK Synchronization of Clock Signals−1. Basic Clock Module Registers Basic Clock Module RegistersRegister Short Form Register Type Address Initial State BCSCTL1, Basic Clock System Control Register DCOCTL, DCO Control RegisterSELMx BCSCTL2, Basic Clock System Control RegisterDIVMx DIVSxIFG1, Interrupt Flag Register IE1, Interrupt Enable Register18Basic Clock Module Chapter Flash Memory Introduction −1. Flash Memory Module Block Diagram−2. Flash Memory Segments, 4-KB Example Flash Memory SegmentationFlash Memory Timing Generator Flash Memory OperationErasing Flash Memory Erase Mode−1. Erase Modes −5. Erase Cycle from Within Flash Memory Initiating an Erase from Within Flash Memory−6. Erase Cycle from Within RAM Initiating an Erase from RAMWriting Flash Memory Write Mode−2. Write Modes Byte/Word Write−8. Initiating a Byte/Word Write from Flash Initiating a Byte/Word Write from Within Flash Memory−9. Initiating a Byte/Word Write from RAM Initiating a Byte/Word Write from RAM−10. Block-Write Cycle Timing Block Write−11. Block Write Flow Block Write Flow and ExampleKHz Smclk 952 kHz Assumes Accvie = Nmiie = Ofie = −3. Flash Access While Busy = Flash Memory Access During Write or EraseFlash ResultStopping a Write or Erase Cycle Configuring and Accessing the Flash Memory ControllerFlash Memory Controller Interrupts Programming Flash Memory DevicesProgramming Flash Memory via Jtag −12. User-Developed Programming Solution−4. Flash Memory Registers Flash Memory RegistersReserved FCTL1, Flash Memory Control RegisterErase Cycle FWKEYx FCTL2, Flash Memory Control RegisterFSSELx FNxFCTL3, Flash Memory Control Register FCTL3 Rather than MOV.B or CLR.B instructions Flash Memory Controller SVS Introduction SVS Operation SVS Registers SVS Introduction −1. SVS Block Diagram SVS Operation Configuring the SVSSVS Comparator Operation Changing the VLDx Bits −2. Svson state When Changing VLDxSVS Operating Range −3. Operating Levels for SVS and Brownout/Reset CircuitSVS Registers Read/write 055h Reset with BOR−1. SVS Registers SVSCTL, SVS Control RegisterSupply Voltage Supervisor Chapter Hardware Multiplier Introduction −1. Hardware Multiplier Block DiagramOperand Registers Hardware Multiplier Operation−1. OP1 addresses OP1 Address Register Name Operation−3. Sumext Contents −2. Reshi ContentsResult Registers Macs Underflow and OverflowProcess results Software ExamplesIndirect Addressing of Reslo Using Interrupts−4. Hardware Multiplier Registers Hardware Multiplier RegistersHardware Multiplier DMA Introduction DMA Operation DMA Registers DMA Introduction −1. DMA Controller Block Diagram DMA Addressing Modes DMA OperationDMA Transfer Modes DMADTx Transfer Description Mode−1. DMA Transfer Modes Single Transfer −3. DMA Single Transfer State Diagram Block Transfers −4. DMA Block Transfer State Diagram Burst-Block Transfers −5. DMA Burst-Block Transfer State Diagram Edge-Sensitive Triggers Initiating DMA TransfersLevel-Sensitive Triggers Halting Executing Instructions for DMA TransfersDMAxTSELx Operation −2. DMA Trigger OperationDMA Channel Priorities Stopping DMA TransfersDMA Priority Transfer Occurs New DMA Priority DMA Transfer Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time−3. Maximum Single-Transfer DMA Cycle Time DMA Controller Interrupts Using DMA with System InterruptsUsing ADC12 with the DMA Controller Using the I2C Module with the DMA ControllerUsing DAC12 With the DMA Controller −4. DMA Registers DMA RegistersTSELx DMACTL0, DMA Control RegisterDMACTL1, DMA Control Register Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMAxCTL, DMA Channel x Control RegisterDMAxSAx DMAxSA, DMA Source Address RegisterDMAxSZ, DMA Size Address Register DMAxDA, DMA Destination Address RegisterPage Chapter Digital I/O Introduction Input Register PxIN Digital I/O OperationOutput Registers PxOUT Direction Registers PxDIRFunction Select Registers PxSEL Interrupt Flag Registers P1IFG, P2IFG 5 P1 and P2 InterruptsConfiguring Unused Port Pins Interrupt Enable P1IE, P2IEInterrupt Edge Select Registers P1IES, P2IES −1. Digital I/O Registers Digital I/O RegistersDigital I/O Watchdog Timer Operation 10-4 Watchdog Timer Introduction 10-2Watchdog Timer Registers 10-7 Watchdog Timer Introduction −1. Watchdog Timer Block Diagram Watchdog Timer Counter Watchdog Timer OperationWatchdog Mode Interval Timer ModeWatchdog Timer Interrupts Software Examples Operation in Low-Power Modes−1.Watchdog Timer Registers Watchdog Timer RegistersWDTISx WDTCTL, Watchdog Timer RegisterNmiie Nmiifg TimerA Operation 11-4 TimerA Introduction 11-2TimerA Registers 11-19 TimerA Introduction −1. TimerA Block Diagram 11.2.1 16-Bit Timer Counter TimerA OperationClock Source Select and Divider Timer Mode Control Starting the Timer−1. Timer Modes MCx Mode Description−2. Up Mode Up Mode−4. Continuous Mode Continuous Mode−6. Continuous Mode Time Intervals Use of the Continuous Mode−7. Up/Down Mode Up/Down Mode−9. Output Unit in Up/Down Mode Use of the Up/Down ModeCapture/Compare Blocks Capture Mode−11. Capture Cycle Compare ModeOutput Unit OUTMODx Mode DescriptionOutput Modes −2. Output Modes−12.Output Example-Timer in Up Mode −13.Output Example-Timer in Continuous Mode −14.Output Example-Timer in Up/Down Mode TACCR0 Interrupt TimerA InterruptsTAIV, Interrupt Vector Generator Taiv Software Example −3. TimerA Registers TimerA RegistersUnused TACTL, TimerA Control RegisterTASSELx IDxTARx TAR, TimerA RegisterCMx TACCTLx, Capture/Compare Control RegisterCCISx OUTMODxTaiv Contents Interrupt Source Interrupt Flag Priority TAIV, TimerA Interrupt Vector RegisterTAIVx Interrupt11-24TimerA TimerB Operation 12-4 TimerB Introduction 12-2TimerB Registers 12-20 Similarities and Differences From TimerA TimerB Introduction−1. TimerB Block Diagram 12.2.1 16-Bit Timer Counter TimerB OperationTBR Length −1.Timer Modes Starting the TimerChanging the Period Register TBCL0 Way as the other capture/compare registers 12-8TimerB TBCL0−1 TBCL0 TBCL0−1 TBCL0−2 Changing the Value of Period Register TBCL0 −10. Capture Signal SCS=1 −11.Capture Cycle −2.TBCLx Load Events TBCLGRPx Grouping Update Control−3.Compare Latch Operating Modes CLLDx Description−4.Output Modes Output Unit−12. Output Example-Timer in Up Mode −13. Output Example-Timer in Continuous Mode −14. Output Example-Timer in Up/Down Mode TBIV, Interrupt Vector Generator TimerB InterruptsTBIV, Interrupt Handler Examples −5.TimerB Registers TimerB RegistersCNTLx TimerB Control Register TbctlTBSSELx TBRx TBR, TimerB RegisterCLLDx TBCCTLx, Capture/Compare Control Register12-24TimerB Tbiv Contents Interrupt Source Interrupt Flag Priority TBIV, TimerB Interrupt Vector RegisterTBIVx 12-26TimerB Usart Operation Uart Mode 13-4 Usart Introduction Uart Mode 13-2Usart Registers Uart Mode 13-21 −1 shows the Usart when configured for Uart mode Usart Introduction Uart Mode−1. Usart Block Diagram Uart Mode Usart Initialization and Reset Usart Operation Uart ModeCharacter Format Idle-Line Multiprocessor Format Asynchronous Communication Formats13-6USART Peripheral Interface, Uart Mode −4. Address -Bit Multiprocessor Format Address-Bit Multiprocessor Format−1.Receive Error Conditions Automatic Error DetectionError Condition Description −5. State Diagram of Receiver Enable Usart Receive Enable−6. State Diagram of Transmitter Enable Usart Transmit Enable−7. MSP430 Baud Rate Generator Uart Baud Rate GenerationDetermining the Modulation Value Baud Rate Bit TimingBrclk = Transmit Bit TimingReceive Bit Timing −9. Receive ErrorBrclk −2.Commonly Used Baud Rates, Baud Rate Data, and Errors Typical Baud Rates and ErrorsUsart Transmit Interrupt Operation Usart Interrupts−11.Receive Interrupt Operation Usart Receive Interrupt OperationReceive-Start Edge Detect Operation −12. Glitch Suppression, Usart Receive Not Started −3.USART0 Control and Status Registers Usart Registers Uart Mode−4.USART1 Control and Status Registers UxCTL, Usart Control Register SSELx UxTCTL, Usart Transmit Control RegisterUxRCTL, Usart Receive Control Register UxBRx UxMCTL, Usart Modulation Control RegisterUxMCTLx UxTXBUF, Usart Transmit Buffer Register UxRXBUF, Usart Receive Buffer RegisterUxRXBUFx Bits UxTXBUFx BitsME2, Module Enable Register ME1, Module Enable RegisterIE2, Interrupt Enable Register IE1, Interrupt Enable RegisterIFG2, Interrupt Flag Register IFG1, Interrupt Flag RegisterUTXIFG0 ‡ Usart Peripheral Interface, Uart Mode 13-31 Usart Operation SPI Mode 14-4 Usart Introduction SPI Mode 14-2Usart Registers SPI Mode 14-13 Usart Introduction SPI Mode −1. Usart Block Diagram SPI Mode Simo Usart Operation SPI ModeFour-Pin SPI Master Mode Master ModeFour-Pin SPI Slave Mode Slave ModeTransmit Enable SPI Enable−6. SPI Master Receive-Enable State Diagram Receive Enable−8. SPI Baud Rate Generator Serial Clock Control−9. Usart SPI Timing Serial Clock Polarity and PhaseSPI Transmit Interrupt Operation SPI InterruptsSPI Receive Interrupt Operation −12. Receive Interrupt State Diagram−1.USART0 Control and Status Registers Usart Registers SPI Mode−2.USART1 Control and Status Registers I2C † UxCTL, Usart Control RegisterCkph Undefined UxRCTL, Usart Receive Control RegisterBaud-rate generator uses the content of UxBR1+UxBR0 to set MSB is always reset USPIE0 † 14-20USART Peripheral Interface, SPI Mode USART0 14-22USART Peripheral Interface, SPI Mode Usart Peripheral Interface, SPI Mode 14-23 2C Module Operation 15-4 2C Module Introduction 15-22C Module Registers 15-20 START/RESTART/STOP 15.1 I2C Module Introduction−1. Usart Block Diagram I 2C Mode 15.2 I2C Module Operation −2. I 2C Bus Connection Diagram15.2.1 I2C Module Initialization −3. I 2C Module Data Transfer 15.2.2 I2C Serial DataBit Addressing 15.2.3 I2C Addressing ModesRepeated Start Conditions −1.Master Operation 15.2.4 I2C Module Operating ModesCondition Or Bus Activity −8. Master Transmitter Mode −9. Master Receiver Mode −10. Arbitration Procedure Between Two Master Transmitters Automatic Data Byte Counting −11.Slave Transmitter −12. Slave Receiver −2.I2CDR Register Function I2C Data Register I2CDRTransmit Underflow Receive Overrun−13. I 2C Module SCL Generation 15.2.6 I2C Clock Generation and SynchronizationUsing the I2C Module with Low Power Modes −3.I 2C Interrupts 15.2.8 I2C InterruptsInterrupt Interrupt Condition Flag I2CIV Software Example I2CIV, Interrupt Vector Generator−4.I 2C Registers 15.3 I2C Module RegistersU0CTL, USART0 Control Register-I2C Mode I2CSSELx I2CTCTL, I2C Transmit Control RegisterUnused I2CDCTL, I2C Data Control RegisterI2CNDAT, I2C Transfer Byte Count Register I2CDRW, I2CDRB, I2C Data RegisterI2CNDATx Bits I2CPSCx I2CPSC, I2C Clock Prescaler RegisterI2CSCLL, I2C Shift Clock Low Register I2CSCLH, I2C Shift Clock High RegisterI2CSCLHx Bits I2CSCLLx BitsI2COA, I2C Own Address Register, 10-Bit Addressing Mode I2COA, I2C Own Address Register, 7-Bit Addressing ModeI2COAx I2CSA, I2C Slave Address Register, 10-Bit Addressing Mode I2CSA, I2C Slave Address Register, 7-Bit Addressing ModeI2CSAx I2CIE, I2C Interrupt Enable Register I2CIFG, I2C Interrupt Flag Register I2CIV I2CIV, I2C Interrupt Vector RegisterI2CIVx 15-32USART Peripheral Interface, I2C Mode ComparatorA Operation 16-4 ComparatorA Introduction 16-2ComparatorA Registers 16-9 ComparatorA Introduction −1. ComparatorA Block Diagram ComparatorA Operation Input Analog SwitchesComparator Voltage Reference Generator Output FilterComparatorA Interrupts ComparatorA, Port Disable Register CapdComparatorA Used to Measure Resistive Elements −5. Temperature Measurement System−6. Timing for Temperature Measurement Systems −1.ComparatorA Registers ComparatorA RegistersCACTL1, ComparatorA Control Register CACTL2, ComparatorA, Control Register CAPD, ComparatorA, Port Disable RegisterCAPDx 16-12ComparatorA ADC12 Operation 17-4 ADC12 Introduction 17-2ADC12 Registers 17-20 17.1 ADC12 Introduction −1. ADC12 Block Diagram 17.2.1 12-Bit ADC Core 17.2 ADC12 OperationConversion Clock Selection Analog Port Selection 17.2.2 ADC12 Inputs and MultiplexerVoltage Reference Generator Auto Power-DownSample and Conversion Timing Extended Sample Mode−4. Pulse Sample Mode Pulse Sample Mode−5. Analog Input Equivalent Circuit Sample Timing ConsiderationsCONSEQx Mode Operation −1.Conversion Mode SummaryConversion Memory 17.2.7 ADC12 Conversion Modes−6. Single-Channel, Single-Conversion Mode Single-Channel Single-Conversion Mode−7. Sequence-of-Channels Mode Sequence-of-Channels Mode−8. Repeat-Single-Channel Mode Repeat-Single-Channel Mode−9. Repeat-Sequence-of-Channels Mode Repeat-Sequence-of-Channels ModeStopping Conversions Using the Multiple Sample and Convert MSC Bit−10. Typical Temperature Sensor Transfer Function Using the Integrated Temperature Sensor−11.ADC12 Grounding and Noise Considerations 17.2.9 ADC12 Grounding and Noise ConsiderationsADC12IV, Interrupt Vector Generator 17.2.10 ADC12 InterruptsADC12IFG15 ADC12 Interrupt Handling Software Example−2.ADC12 Registers 17.3 ADC12 RegistersSHT1x ADC12CTL0, ADC12 Control RegisterSHT0x Bit Reference generator voltage. Refon must also be set ADDx ADC12CTL1, ADC12 Control RegisterSHSx ADC12DIVxCONSEQx ADC12MEMx, ADC12 Conversion Memory RegistersConversion ResultsSREFx ADC12MCTLx, ADC12 Conversion Memory Control RegistersINCHx ADC12IFG, ADC12 Interrupt Flag Register ADC12IE, ADC12 Interrupt Enable RegisterADC12IEx ADC12IFGx BitsADC12IV, ADC12 Interrupt Vector Register Contents Interrupt Source Interrupt Flag PriorityADC12IVx Bits 17-28 ADC12 ADC10 Operation 18-4 ADC10 Introduction 18-2ADC10 Registers 18-24 18.1 ADC10 Introduction −1. ADC10 Block Diagram 18.2.1 10-Bit ADC Core 18.2 ADC10 OperationAnalog Port Selection 18.2.2 ADC10 Inputs and MultiplexerVoltage Reference Generator Internal Reference Low-Power Features−3. Sample Timing −4. Analog Input Equivalent Circuit Conversion Modes −1.Conversion Mode Summary−5. Single-Channel Single-Conversion Mode −6. Sequence-of-Channels Mode −7. Repeat-Single-Channel Mode −8. Repeat-Sequence-of-Channels Mode Stopping Conversions Using the MSC Bit18.2.7 ADC10 Data Transfer Controller −9. One-Block Transfer One-Block Transfer Mode=0 ADC10DTC1 DTC reset Wait for write to −11.Two-Block Transfer Two-Block Transfer ModeADC10CT=1 Continuous Transfer CPU Operating Mode Clock Source Maximum DTC Cycle TimeDTC Transfer Cycle Time −2.Maximum DTC Cycle Time−14. Typical Temperature Sensor Transfer Function −16. ADC10 Grounding and Noise Considerations 18.2.9 ADC10 Grounding and Noise Considerations−17. ADC10 Interrupt System 18.2.10 ADC10 Interrupts−3.ADC10 Registers 18.3 ADC10 RegistersSHTx ADC10CTL0, ADC10 Control RegisterBit Reference-generator voltage. Refon must also be set INCHx ADC10CTL1, ADC10 Control RegisterADC10DIVx ADC10AE, Analog Input Enable Control RegisterADC10AEx Bits ADC10MEM, Conversion-Memory Register, 2’s Complement Format ADC10MEM, Conversion-Memory Register, Binary FormatReserved ADC10DTC0, Data Transfer Control RegisterADC10SA, Start Address Register for Data Transfer ADC10DTC1, Data Transfer Control RegisterTransfers ADC10SAx18-32 ADC10 DAC12 Operation 19-4 DAC12 Introduction 19-2DAC12 Registers 19-10 19.1 DAC12 Introduction −1. DAC12 Block Diagram 19.2.1 DAC12 Core 19.2 DAC12 Operation−1.DAC12 Full-Scale Range Vref = V eREF+ or VREF+ DAC12 Port SelectionDAC12 Reference Input and Voltage Output Buffers 19.2.2 DAC12 ReferenceUpdating the DAC12 Voltage Output 19.2.4 DAC12xDAT Data Format −4. Negative Offset 19.2.5 DAC12 Output Amplifier Offset CalibrationGrouping Multiple DAC12 Modules −6. DAC12 Group Update Example, TimerA3 Trigger19.2.7 DAC12 Interrupts −2.DAC12 Registers 19.3 DAC12 RegistersLSELx DAC12xCTL, DAC12 Control RegisterAMPx DAC12AMPx Input Buffer Output BufferDAC12 Data DAC12xDAT, DAC12 Data RegisterDAC12 Data Format 19-14 DAC12