13. I 2C Module SCL Generation | Texas Instruments MSP430x1xx

I2C Module Operation

15.2.6 I2C Clock Generation and Synchronization

The I2C module is operated with the clock source selected by the I2CSSELx bits. The prescaler, I2CPSC, and the I2CSCLH and I2CSCLL registers determine the frequency and duty cycle of the SCL clock signal for master mode as shown in Figure 15−13.

Note: I2CCLK Maximum Frequency

The I2C module clock source I2CIN must be at least 10x the SCL frequency in both master and slave modes. This condition is met automatically in master mode by the I2CSCLL and I2CSCLH registers.

Note: I2CPSC Value

When I2CPSC > 4, unpredictable operation can result. The I2CSCLL and

I2CSCLH registers should be used to set the SCL frequency.

Figure 15−13. I 2C Module SCL Generation

I2CIN

I2CPSC

I2CCLK

(I2CPSC +2) x (I2CSCLH + 1) (I2CPSC + 2) x (I2CSCLL + 1)

During the arbitration procedure the clocks from the different masters must be synchronized. A device that first generates a low period on SCL overrules the other devices forcing them to start their own low periods. SCL is then held low by the device with the longest low period. The other devices must wait for SCL to be released before starting their high periods. Figure 15−14 illustrates the clock synchronization. This allows a slow slave to slow down a fast master.

Figure 15−14. Synchronization of Two I 2C Clock Generators During Arbitration

Wait

State Start HIGH

Period

SCL From

Device #1

SCL From

Device #2

Bus Line

SCL

15-16USART Peripheral Interface, I2C Mode

MSP430x1xx specifications

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Texas Instruments MSP430x1xx manual 15.2.6 I2C Clock Generation and Synchronization

Models: MSP430x1xx

15.2.6 I2C Clock Generation and Synchronization

Figure 15−13. I 2C Module SCL Generation

Figure 15−14. Synchronization of Two I 2C Clock Generators During Arbitration

MSP430x1xx specifications