Texas Instruments SM320C6455-EP manuals
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Texas Instruments SM320C6455-EP Manual
254 pages 2.12 Mb
3 ContentsSM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR 4 SM320C6455-EP5 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR6 SM320C6455-EP20 SM320C6455-EP45 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR2.8 Development 2.8.1 Development Support 2.8.2 Device Support 55 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR64 SM320C6455-EPDevice Configuration64 Submit Documentation Feedback 65 3.4 Device State Control RegistersNOTEThe device state control registers can only be accessed using the CPU or the emulator. Table 3-5. Device State Control Registers 66 3.4.1 Peripheral Lock Register Description67 3.4.2 Peripheral Configuration Register 0 Description69 3.4.3 Peripheral Configuration Register 1 Description70 3.4.4 Peripheral Status Registers Description73 3.4.5 EMAC Configuration Register (EMACCFG) Description74 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description75 3.5 Device Status Register Description77 3.6 JTAG ID (JTAGID) Register DescriptionTable 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) 78 3.7 Pullup/Pulldown Resistors3.8 Configuration Examples 81 4 System Interconnect87 5 C64x+ Megamodule101 6 Device Operating Conditions105 7 C64x+ Peripheral Information and Electrical Specifications7.1 Parameter Information 7.1.2 3.3-V Signal Transition Rates 7.1.1 3.3-V Signal Transition Levels 106 7.1.3 Timing Parameters and Board Routing AnalysisFigure 7-4. Board-Level Input/Output Timings 107 7.3.2 Power-Supply Decoupling7.3.3 Power-Down Operation 108 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins109 7.4 Enhanced Direct Memory Access (EDMA3) Controller110 7.4.1 EDMA3 Device-Specific Information7.4.2 EDMA3 Channel Synchronization Events 111 7.4.3 EDMA3 Peripheral Register Description(s)124 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller127 7.5.2 External Interrupts Electrical Data/TimingTable 7-11. Timing Requirements for External Interrupts (see Figure 7-6 ) Figure 7-6. NMI Interrupt Timing 128 7.6 Reset Controller7.6.1 Power-on Reset ( POR Pin) 129 7.6.2 Warm Reset ( RESET Pin)130 7.6.3 Max Reset 7.6.4 System Reset7.6.5 CPU Reset 131 7.6.6 Reset Priority132 7.6.7 Reset Controller Register7.6.7.1 Reset Type Status Register Description 133 7.6.8 Reset Electrical Data/Timing137 7.7.1 PLL1 Controller Device-Specific Information7.7.1.1 Internal Clocks and Maximum Operating FrequenciesSubmit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 137 A. DIVIDER D2 and DIVIDER D3 are always enabled. B. CLKIN1 is a 3.3-V signal. 139 7.7.2 PLL1 Controller Memory Map140 7.7.3 PLL1 Controller Register Descriptions150 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/TimingTable 7-29. Timing Requirements for CLKIN1 Devices (see Figure 7-21 ) (see Figure 7-22 ) Figure 7-22. SYSCLK4 Timing 151 7.8 PLL2 and PLL2 ControllerSubmit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 151 Figure 7-23. PLL2 Block Diagram 152 7.8.1 PLL2 Controller Device-Specific Information153 7.8.2 PLL2 Controller Memory Map7.8.3 PLL2 Controller Register Descriptions 159 7.8.4 PLL2 Controller Input Clock Electrical Data/TimingTable 7-39. Timing Requirements for CLKIN2 (see Figure 7-30 ) Figure 7-30. CLKIN2 Timing 160 7.9 DDR2 Memory Controller7.9.1 DDR2 Memory Controller Device-Specific Information 161 7.9.2 DDR2 Memory Controller Peripheral Register Description(s)7.9.3 DDR2 Memory Controller Electrical Data/TimingTable 7-40. DDR2 Memory Controller Registers 162 7.10 External Memory Interface A (EMIFA)7.10.1 EMIFA Device-Specific Information 163 7.10.2 EMIFA Peripheral Register Description(s)Table 7-41. EMIFA Registers 164 7.10.3 EMIFA Electrical Data/Timing171 7.10.4 HOLD/ HOLDA TimingTable 7-48. Timing Requirements for the HOLD/ HOLDA Cycles for EMIFA Module (see Figure 7-39 ) (see Figure 7-39 ) Figure 7-39. HOLD/ HOLDA Timing for EMIFA 172 7.10.5 BUSREQ TimingFigure 7-40. BUSREQ Timing for EMIFA 173 7.11 I2C Peripheral 7.11.1 I2C Device-Specific Information175 7.11.2 I2C Peripheral Register Description(s)Table 7-51. I2C Registers 176 7.11.3 I2C Electrical Data/Timing179 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information7.12.2 HPI Peripheral Register Description(s) 180 7.12.3 HPI Electrical Data/Timing191 7.13.1 McBSP Device-Specific Information193 7.13.2 McBSP Electrical Data/Timing7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP Table 7-59. Timing Requirements for McBSP (see Figure 7-52 ) 195 Figure 7-52. McBSP TimingSubmit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 195 Table 7-61. Timing Requirements for FSR When GSYNC = 1 (see Figure 7-53 )-720 -850A-1000/-1000NO. UNIT-1200 MIN MAX 1 t Setup time, FSR high before CLKS high 4 ns 2 t Hold time, FSR high after CLKS high 4 ns Figure 7-53. FSR Timing When GSYNC = 1 196 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(see Figure 7-54 ) (see Figure 7-54 ) Figure 7-54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 197 Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(see Figure 7-55 ) (see Figure 7-55 ) Figure 7-55. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 198 Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1(see Figure 7-56 ) (see Figure 7-56 ) Figure 7-56. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 199 Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1(see Figure 7-57 ) (see Figure 7-57 ) Figure 7-57. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 200 7.14 Ethernet MAC (EMAC)201 7.14.1 EMAC Device-Specific Information204 7.14.2 EMAC Peripheral Register Description(s)208 7.14.3 EMAC Electrical Data/Timing216 7.14.4 Management Data Input/Output (MDIO)218 7.15 Timers 7.15.1 Timers Device-Specific Information7.15.2 Timers Peripheral Register Description(s)Table 7-93. Timer 1 Registers 219 7.15.3 Timers Electrical Data/TimingTable 7-94. Timing Requirements for Timer Inputs Table 7-95. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs (see Figure 7-73 ) Figure 7-73. Timer Timing 220 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) 7.16.1 VCP2 Device-Specific Information7.16.2 VCP2 Peripheral Register Description(s) 221 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.1 TCP2 Device-Specific Information222 7.17.2 TCP2 Peripheral Register Description(s)Table 7-97. TCP2 Registers 223 7.18 Peripheral Component Interconnect (PCI)7.18.1 PCI Device-Specific Information 224 7.18.2 PCI Peripheral Register Description(s)230 7.19 UTOPIA 7.19.1 UTOPIA Device-Specific Information7.19.2 UTOPIA Peripheral Register Description(s)Table 7-105. UTOPIA Data Queues (Receive and Transmit) Registers 231 7.19.3 UTOPIA Electrical Data/Timing234 7.20 Serial RapidIO (SRIO) Port7.20.1 Serial RapidIO Device-Specific Information 7.20.2 Serial RapidIO Peripheral Register Description(s) 244 7.20.3 Serial RapidIO Electrical Data/Timing247 7.21.3 GPIO Electrical Data/TimingTable 7-114. Timing Requirements for GPIO Inputs Table 7-115. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 7-78 ) Figure 7-78. GPIO Port Timing 249 7.22.3 IEEE 1149.1 JTAG7.22.3.1 JTAG Device-Specific Information 7.22.4 JTAG Peripheral Register Description(s) 7.22.5 JTAG Electrical Data/TimingTable 7-116. Timing Requirements for JTAG Test Port (see Figure 7-79 ) Figure 7-79. JTAG Test-Port Timing 250 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version. 251 8 Mechanical Data8.1 Thermal Data 8.2 Packaging Information PACKAGING INFORMATION 252 PACKAGE OPTION ADDENDUM
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