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The BladeCenter HS20 uses the IntelĀ® Lindenhurst chipset (see the HS20 architecture in Figure
8843 HS20 Block Diagram |
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limitations this |
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VRM |
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diagram is not |
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drawn to scale | To SP I2C bus |
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| Data A | To SP I2C bus | |||||
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| Hublink 1.5 | MCH | Data B |
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| LPC |
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PCI |
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bus 0 |
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| x8 | To SP |
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| I2C bus |
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| sockets | ||
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| PCIExpress |
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PCIX 66 | PCI Express x4 |
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| EEPROM |
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| I2C bus | Renassas |
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| PXH |
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| SP (2166) |
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LSI |
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1020 |
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SCSI |
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| Video |
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| PCIX B |
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| 1Gb Ethernet | 1 Gb | ||
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| Daughter card connector |
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| Ethernet | ||
SCSI HDD Connector 1 | Blade |
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| Expansion |
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| Midplane HD | Midplane HD | ||||
SCSI HDD Connector 1 | Connector |
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| connector A | connector B | ||
Figure |
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The Intel Lindenhurst chipset consists of the following components:
ļææMemory and I/O controller (MCH) (North Bridge)
ļææPXH-D
ļææ
The Lindenhurst MCH, Memory and I/O controller provides the interface between the processors, the memory, and the PCI Express busses that interface to the other Intel chips. The Lindenhurst
The LPC bus is used to connect to the POST/BIOS EEPROM on the 8843. The size of the EEPROM is 4 MB x 8, and it contains primary BIOS, backup BIOS, and blade diagnostics.
Chapter 2. IBM Eserver BladeCenter overview 11