Kawasaki 80C152, 80C51 technical specifications Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2

KS152JB Universal Communications Controller Technical Specifications

GREN has no effect on whether the receiver detects a collision in CSMA/CD mode as the receiver input circuitry always monitors the receive pin.

RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set, indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive data is loaded. A CPU read of the FIFO retrieves the oldest data and automatically updates the FIFO pointers. Setting GREN to a one will clear the receive FIFO. The status of this flag is controlled by the GSC. This bit is cleared if the user software empties receive FIFO.

RSTAT.3 (RDN) - Receive Done - If set, indicates the successful completion of a receiver opera- tion. Will not ne set is a CRC, alignment, abort or FIFO overrun error occurred.

RSTAT.4 (CRCE) - CRC Error - If set, indicates that a properly aligned frame was received with a mismatched CRC.

RSTAT.5 (AE) - Alignment Error - In CSMA/CD mode, AE is set if the receiver shift register (an internal serial-to-parallel converter) is not full and CRC is bad when an EOF is detected. In CSMA/ CD the EOF is a line idle condition (see LNI) for two bit times. If the CRC is correct while in CSMA/CD mode, AE bit is not set and any mis-alignment us assumed to be caused by dribble bits as the line went idle. in SDLC mode. AE is set if a non-byte-aligned flag is received. CRC may also be set. The setting of this flag is controlled by the GSC.

RSTAT.6 (RCABT) - Receiver Collision/Abort Detect - If set, indicates a collision was detected after data had been loaded into the receive FIFO in CSMA/CD mode. In SDLC mode, RCABT indicates that 7 consecutive 1’s were detected prior to the end of flag but after data has been loaded into the receive FIFO. AE may also be set if RCABT is set.

RSTAT.7 (OVR) - Overrun - If set, indicates that the receive FIFO was full and new shift register data was written into it. It is cleared by the user software. AE and/or CRCE may also be set if OVR is set.

SARH0 (0A3H) - Source Address Register High 0, contains the high byte of the source address for the DMA Channel 0.

SARH1 (0B3H) - Source Address Register High 1, contains the high byte of the source address for the DMA Channel 1.

SARL0 (0A2H) - Source Address Register Low 0, contains the low byte of the source address for the DMA Channel 0.

SARL1 (0B2H) - Source Address Register Low 1, contains the low byte of the source address for the DMA Channel 1.

SAS - Source Address Space bit, see DCON0.

SBUF (099H) - Serial Buffer, both the receive and transmit SFR location for the LSC.

Kawasaki LSI USA, Inc. Page 108 of 120 Ver. 0.9 KS152JB2