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Kawasaki 80C51, KS152JB, 80C152 technical specifications Timer/Counter in Mode

Models: 80C51 KS152JB 80C152

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KS152JB Universal Communications Controller Technical Specifications

OSC

S3P1

C/T

Tx pin

TRx

GATE

INTx pin

I0

I1

Q

TLX

5 bits

THx

8 bits

TFx

INTERRUPT

Timer/Counter in Mode 0

MODE 1

Mode 1 is similar to Mode 0 except that the counting register form a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used.

.

OSC

S3P1

C/T

Tx pin

TRx

GATE

INTx pin

I0

I1

Q

TLX

8 bits

Reload

THx

8 bits

TFx

INTERRUPT

Timer/Counter in Mode 2

MODE 2

In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count register, while THx holds the reload value. When the TLx register overﬂows from FFh to 00h, the TFx bit in TCON is set and TLx is reloaded with the contents of THx and the counting process continues from here. The reload operation leaves the contents of the THx register unchanged

MODE 3

Mode 3 has different operating methods for the two timer/counters. For timer/counter TM1, mode 3 simply freezes the counter. This is the same as setting TR1 to 0.

Timer/Counter TM0 however conﬁgures TL0 and TH0 as two separate 8 bit count registers in this mode. The logic for this mode is shown in the ﬁgure. TL0 uses the Timer/Counter TM0 control bits C/T, GATE, TR0, INT0 and TF0. TH0 is forced as a machine cycle counter and takes over the use of TR1 and TF1 from Timer/Counter TM1.

Kawasaki LSI USA, Inc.

Page 14 of 120

Ver. 0.9 KS152JB2

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Kawasaki 80C51, KS152JB, 80C152 technical specifications Timer/Counter in Mode

Contents

Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate FunctionRST XTAL1XTAL2 Eben ALEPsen EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Comments ProgramPsen Epsen Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPgsrv PX0EX0 Egsrv 2BHPT1 PDMA1EDMA1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter ToleranceUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive TfifoAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring NetworkSdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Deﬁned ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryRcbat Crce Determining Receiver ErrorsExternal Clocking AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISASerial Port Demand Mode External Demand ModePCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal MemoryDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode Using the HOLD/HLDA Acknowledge ARB REQDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPHTimer 0 LSB Timer Mode ControlGate Timer Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Data Buffer Serial Port ControlSM0 SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2