KS152JB Universal Communications Controller Technical Specifications
The functions of the ARB and REQ bits in PCON, then, are
ARB | REQ | Hold/Hold Acknowledge Logic |
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0 | 0 | Disabled |
0 | 1 | C152 generates HLD, detects HLDA |
1 | 0 | C152 detects HLD, generates HLDA |
1 | 1 | Invalid |
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4.3.3 USING THE HOLD/HLDA ACKNOWLEDGE
The HOLD/HOLDA logic only affects DMA operation with external RAM and don’t affect other operations with external RAM, such as MOVX instruction.
Figure shows a system in which two 83C152s are sharing a global RAM. In this system, both CPUs are executing from internal ROM. Neither CPU uses the bus except to access the shared RAM, and such accesses are done only through DMA operations, not by MOVX instructions.
Two 83C152s Sharing External RAM
| 8 X 10 kohms |
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| P0 |
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83C152 |
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ARB |
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| P2 |
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WR | ALE | 7 |
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4 |
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RD |
| L |
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| S |
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| 3 |
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HLD | HLDA | 7 |
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3 |
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HLD | ALE SWITCH |
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HLDA |
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| ALE |
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83C152 |
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REQ P0 |
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WR |
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| P2 |
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RD |
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| DATA | LOW | HIGH |
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| SHARED RAM | |
| OE |
| ADDR |
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| WE |
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One CPU is programmed to be the Arbiter and the other, to be the Requester. The ALE Switch
Kawasaki LSI USA, Inc. | Page 83 of 120 | Ver. 0.9 KS152JB2 |
