Arb Req, Using the HOLD/HLDA Acknowledge | Kawasaki 80C51, KS152JB

KS152JB Universal Communications Controller Technical Specifications

The functions of the ARB and REQ bits in PCON, then, are

ARB	REQ	Hold/Hold Acknowledge Logic

0	0	Disabled
0	1	C152 generates HLD, detects HLDA
1	0	C152 detects HLD, generates HLDA
1	1	Invalid

4.3.3 USING THE HOLD/HLDA ACKNOWLEDGE

The HOLD/HOLDA logic only affects DMA operation with external RAM and don’t affect other operations with external RAM, such as MOVX instruction.

Figure shows a system in which two 83C152s are sharing a global RAM. In this system, both CPUs are executing from internal ROM. Neither CPU uses the bus except to access the shared RAM, and such accesses are done only through DMA operations, not by MOVX instructions.

Two 83C152s Sharing External RAM

	8 X 10 kohms
	P0
83C152
ARB
	P2
WR	ALE	7
WR	ALE	4
		4
RD		L
RD		S
		S
		3
HLD	HLDA	7
HLD	HLDA	3
		3
HLD	ALE SWITCH
HLD	HLDA
	ALE
83C152
REQ P0
WR
	P2
RD
	DATA	LOW	HIGH
		SHARED RAM
	OE		ADDR
	OE
	WE

One CPU is programmed to be the Arbiter and the other, to be the Requester. The ALE Switch

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Kawasaki 80C51, KS152JB, 80C152 technical specifications Arb Req, Using the HOLD/HLDA Acknowledge

Contents

Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description Port RST XTAL1XTAL2 Epsen ALEPsen Eben SFR map for the cpu Special function Registers Reset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate Tmod Port bit I/O Pads Port 0 I/O Pad Port 2 I/O Pad Ports 4,5 Fetch via ProgramPsen Epsen Comments Tmod Timer/Counter Mode Control Register TIMER/COUNTERS Mode Tcon Timer/Counter Control Register Timer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre Egsrv Egsrv 2BH PX0EX0 Pgsrv ET1 1BH PDMA1EDMA1 PT1 Kawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Smod IDL Pcon Power Control Register Local Serial Channel Controller Local Serial Port Mode Serial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Introduction Global Serial Channel DC JAM CRC 11/IDLE CRC None 11/IDLE Csma Sdlc External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision Detection Unexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doing Algorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop Network User Deﬁned Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc Hdlc Planning for Network Changes and Expansions Line Discipline DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test Modes Jitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time Received CSMA/CD Clock Recovery Receiver Clock Recovery Addressing Determining Receiver ErrorsExternal Clocking Rcbat Crce 2 CPU/DMA Control of the GSC Determining Line Discipline Collisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register Descriptions PL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0 Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA Operation DMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDA External Demand Mode Serial Port Demand Mode DMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program Execution DMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode ARB REQ Using the HOLD/HLDA Acknowledge Dmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control Bits Interrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RI IPN1 PT1 PX1 PT0 PX0 Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error Conditions GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOW DPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSB Timer 1 MSB Timer 0 MSB SBUF.7 Serial Port ControlSM0 Serial Data Buffer RS1 RS0 Program Status Word ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Accumulator Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2