Kawasaki 80C51, KS152JB, 80C152 technical specifications DMA Arbitration

KS152JB Universal Communications Controller Technical Specifications

If the DMA is in alternate cycles mode, then each time DMA cycle is completed DMXRQ goes to 0, thus de-activating HLD. Once HLD has been de-activate, it can’t be re-asserted till after HLDA has been to go high (through flip-flop Q1A). Thus every time the DMA is suspended to allow an instruction cycle to proceed, the requester gives up the bus and must renew the request and receive another acknowledge before another DMA cycle to XRAM can proceed. Obviously in this case, the “alternate cycles” mode may consist of single DMA cycles separated by any number of instruction cycles, depending on how long it takes the requester to regain the bus.

A channel 1 DMA in progress will always be overridden by a DMA request of any kind from channel 0. If a channel 1 DMA to XRAM is in progress and is over-ridden by a channel 0 DMA which does not require the bus, DMXRQ will go to 0 during the channel 0 DMA, thus de-activat- ing HLD. Again, the requester must re-new its request for the bus, and must receive a new 1-to-0 transition in HLDA before channel 1 can continue its DMA to XRAM.

4.4 DMA Arbitration

The DMA Arbitration described in this section is not arbitration between two devices wanting to access a shared RAM, but on-chip arbitration between the two DMA channels on the 8XC152.

The 8XC152 provides two DMA channels, either of which may be called into operation at any time in response to real time conditions in the application circuit. Since a DMA cycle always uses the 8XC152’s internal bus, and there’s only one internal bus, only one DMA channel can be ser- viced during a single DMA cycle. Executing program instructions also requires the internal bus, so program execution will also be suspended in order for a DMA to take place.

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0	ARBITRA-	2
	TION
	LOGIC
DMAO	DMA 1	INSTRUCTION
CYCLE	CYCLE	CYCLE
		WRITE	YES
		TO
		DMA
		REG?
		NO

Figure above shows the three tasks to which the internal bus of the 8XC152 can be dedicated. In this figure, Instruction Cycle means the complete execution of a single instruction, whether it takes 1,2 or 4 machine cycles. DMA Cycle means the transfer of a single data byte from source to destination, whether it takes 1 or 2 machine cycles. Each time a DMA Cycle or an Instruction

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