Resolution of Collisions, GSC Inactive, Tfifo | Kawasaki 80C152

KS152JB Universal Communications Controller Technical Specifications

3.2.6 RESOLUTION OF COLLISIONS

How the GSC responds to a detected collision depends on what it was doing at the time the colli- sion was detected. What it might be doing is either transmitting or receiving a frame, or it might be inactive.

GSC Inactive

If the GSC is already in the process of receiving a frame at the time the collision is detected, its response depends on whether the ﬁrst byte of the frame has been transferred into RFIFO yet or not. If that hasn’t occurred, the GSC simply aborts the reception, but takes no other action unless DCR has been selected. If DCR has been selected, the GSC participates in the resolution algo- rithm.

If the reception has already progressed to the point where a byte has been transferred to RFIFO by the time the collision is detected, the receiver is disabled (GREN = 0), and the Receive Error Interrupt ﬂag RCABT is set. If DCR has been selected, the GSC participates in the resolution algorithm.

Table 11: Response to a Detected Collision.

What the GSC was doing	Response

nothing	None, Unless DCR =1.
	If DCR = 1, begin DCR countdown

Receiving a Frame, ﬁrst byte not in RFIFO yet.	None, unless DCR = 1.
	If DCR = 1, begin DCR countdown.

Receiving a Frame, ﬁrst byte already in RFIFO.	Set RCABT, clear GREN.
	If DCR = 1, begin DCR countdown.

Transmitting a Frame, ﬁrst byte still in TFIFO	Execute jam/backoff.
	Restart if collision count< 8.

Transmitting a Frame, ﬁrst byte already taken from	Execute jam/backoff.
TFIFO	Set TCDT, clear TEN.

Note: References to DCR and the DCR Countdown have to do with the Deterministic Colli- sion Resolution Algorithm.

Jam

The jam signal is generated by any 8XC152 that is involved in transmitting a frame at the time a collision is detected at its GRXD pin. This is to ensure that if one transmitting station detects a collision, all the other stations on the network will also detect a collision.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Kawasaki 80C152 Resolution of Collisions, GSC Inactive, Response to a Detected Collision What the GSC was doing, Tfifo

Contents

Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description Port XTAL2 XTAL1RST Epsen ALEPsen Eben SFR map for the cpu Special function Registers Reset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate Tmod Port bit I/O Pads Port 0 I/O Pad Port 2 I/O Pad Ports 4,5 Fetch via ProgramPsen Epsen Comments Tmod Timer/Counter Mode Control Register TIMER/COUNTERS Mode Tcon Timer/Counter Control Register Timer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre Egsrv Egsrv 2BH PX0EX0 Pgsrv ET1 1BH PDMA1EDMA1 PT1 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Smod IDL Pcon Power Control Register Local Serial Channel Controller Local Serial Port Mode Serial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Introduction Global Serial Channel DC JAM CRC 11/IDLE CRC None 11/IDLE Csma Sdlc External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision Detection Missing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doing DCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop Network User Deﬁned Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc Hdlc Planning for Network Changes and Expansions Line Discipline DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test Modes Jitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time Received CSMA/CD Clock Recovery Receiver Clock Recovery Addressing Determining Receiver ErrorsExternal Clocking Rcbat Crce 2 CPU/DMA Control of the GSC Determining Line Discipline Collisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register Descriptions PL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0 Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA Operation DMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDA External Demand Mode Serial Port Demand Mode DMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program Execution DMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA Acknowledge Internal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control Bits Interrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RI IPN1 PT1 PX1 PT0 PX0 Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error Conditions GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOW DPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSB Timer 1 MSB Timer 0 MSB SBUF.7 Serial Port ControlSM0 Serial Data Buffer RS1 RS0 Program Status Word ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Accumulator Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2