DMA Operation, DMA with the 80C152 | Kawasaki KS152JB, 80C51

KS152JB Universal Communications Controller Technical Specifications

4.0 DMA Operation

The C152 contains DMA (Direct Memory Accessing) logic to perform high speed data transfers between any two of

Internal Data RAM

Internal SFRs

External Data RAM

In external RAM is involved, the Port 2 and Port 0 pins are used as the address/data bus, and RD and WR signals are generated as required.

Hardware is also implemented to generate a Hold Request signal and await a Hold Acknowledge response before commencing a DMA that involves external RAM.

Alternatively, The Hold/Hold Acknowledge hardware can be programed to accept a Hold Request signal from an external device and generate a Hold Acknowledge signal in response, to indicate to the requesting device that the C152 will not commence a DMA to or from external RAM while the Hold Request is active.

4.1 DMA with the 80C152

The C152 contains two identical general purpose 8-it DMA channels with 16-bit address ability: DMA0 and DAM1. DMA transfers can be executed by either channel independent of the other, but only by one channel at a time. During the time that a DMA transfer is being executed, pro- gram execution is suspended. A DMA transfer takes one machine cycle (12 oscillator periods) per byte transferred, except when the destination and source are both in External Data RAM. In that case the transfer takes two machine cycles per byte. The term DMA Cycle will be used to mean the transfer of a single data byte, whether it takes 1 or 2 machine cycles.

Associated with each channel are seven SFRs, shown below SARLn and SARHn holds the low and high bytes of the source address. Taken together they form a 16-bit Source Address Register. DARLn and DARHn hold the low and high bytes of the destination address, and together form the Destination Address Register. BCRLn and BCRHn hold the low and high bytes of the number of bytes to be transferred, and together form the Byte Count Register. DCONn contains control and ﬂag bits.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Kawasaki KS152JB, 80C51 technical specifications DMA Operation, DMA with the 80C152

Contents

Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate Function XTAL2 XTAL1RST ALE PsenEben Epsen Special function Registers SFR map for the cpu Reset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod Pcon Port 0 I/O Pad Port 2 I/O Pad Port bit I/O Pads Ports 4,5 Program Psen EpsenComments Fetch via TIMER/COUNTERS Tmod Timer/Counter Mode Control Register Tcon Timer/Counter Control Register Mode Timer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv PX0 EX0Pgsrv Egsrv 2BH PDMA1 EDMA1PT1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Pcon Power Control Register Smod IDL Local Serial Channel Local Serial Port Mode Controller Serial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRC Csma Sdlc 11/IDLE External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter Tolerance Missing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing Tfifo DCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring Network Using a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Deﬁned Protocols Line Discipline Planning for Network Changes and Expansions DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver Interface Jitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit Waveforms Receiver Clock Recovery CSMA/CD Clock Recovery Determining Receiver Errors External ClockingRcbat Crce Addressing Determining Line Discipline 2 CPU/DMA Control of the GSC Collisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and Receptions GMOD84H Xtclk PL1 PL0 PL1 PL0 Length Bits Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDL Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152 DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISA Serial Port Demand Mode External Demand Mode Timing Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory DMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQ Internal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA Done Interrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 IPN1 GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPH Timer Mode Control Gate TimerTimer 0 LSB Timer 1 LSB Timer 0 MSB Timer 1 MSB Serial Port Control SM0Serial Data Buffer SBUF.7 Program Status Word RS1 RS0 Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2