Kawasaki 80C152, 80C51 technical specifications Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2

KS152JB Universal Communications Controller Technical Specifications

Cycle is executed, on-chip arbitration logic determines which type of cycle is to be executed next.

Note that when an instruction is executed, if the instruction wrote to a DMA register (excluding PCON), then another instruction is executed without further arbitration. Therefore, a single write or a series of writes to DMA registers will prevent a DMA from taking place, and will continue to prevent a DMA from taking place until at least one instruction is executed which does not write to any DMA register.

The logic that determines whether the next cycle will be a DMA0 cycle, a DMA1 cycle, or an Instruction Cycle is shown as a pseudo-HLL function. The statements are executed sequentially unless an “if” condition is satisfied, in which case the corresponding “return” is executed and the remainder of the function is not. The return value of 0,1, or 2 is passed to the arbitration logic block to determine which exit path from the block is used.

arbitration_logic	:
if (G00	= 1.AND. mode_logic (0) = 1) return 0;

else if (G01 = 1.AND. mode_logic (1) = 1) return 1; else return 2;

end arbitration_logic;

Kawasaki LSI USA, Inc.oup, Inc. Page 87 of 120 Ver. 0.9 KS152JB2