KS152JB Universal Communications Controller Technical Specifications
Some of the general areas that will impact the overall scheme on how to incorporate future changes to the system are:
1)Communication of the change to all the stations or the primary station.
2)Maximum distance for communication. This will affect the drivers used and the slot time.
3)More stations may be on the line at one time. This may impact the interframe space or the col- lision resolution used.
4)If using CSMA/CD without deterministic resolution, any increase in network size will have a negative impact on the average throughput of the network and lower the efficiency. The user will have to give careful consideration when deciding how large a system can ultimately be and still maintain adequate performance.
3.5.3 DMA SERVICING OF GSC CHANNELS
There are two sources that can be used to control the GSC. The first is CPU control and the sec- ond is DMA control.
CPU control is used when user software takes care of the tasks such as: loading the TFIFO, read- ing the RDIFO, checking the status flags, and general tracking of the transmission process. As the number of tasks grow and higher data transfer rates are used, the overhead required by the CPU becomes the dominant consumption of time. Eventually, a point is reached where the CPU is spending 100% of its time responding to the needs of the GSC. An alternative is to have the DMA channels control the GSC
A detailed explanation on the general use of the DMA channels is covered in Section 4. In this section only those details required for the use of the DMA channels with the GSC will be covered.
The DMA channels can be configured by user software so that the GSC data transfers are serviced by the DA controller. Since there are two DMA channels, one channel can be used to service the receiver, and one channel can be used to service the transmitter. In using the DMA channels, the CPU is relived of much of the time required to do the basic servicing of the GSC buffers. The types of servicing that the DMA channels can provide are: loading of the transmit FIFO, remov- ing data from the receive FIFO, notification of the CPU when the transmission or reception has ended, and response to certain error conditions. When using the DMA channels the source or des- tination of the data intended for serial transmission can be internal data memory, external data memory, or any of the SFRs.
The only tasks required after initialization of the DMA and GSC registers are enabling the proper interrupts and informing the DMA controller when to start. After the DMA channels are started all that is required of the CPU is to respond to error conditions or wait until the end of transmis- sion.
Initialization of the DMA channels requires setting up the control, source, and destination address
Kawasaki LSI USA, Inc. | Page 56 of 120 | Ver. 0.9 KS152JB2 |
