Ti+Ri, ET1 EX1 ET0 EX0 | Kawasaki 80C152, KS152JB, 80C51 guide

KS152JB Universal Communications Controller Technical Specifications

		Table 14:

Interrupt	Location		Name


DMA1	0053H		DMA Channel 1 Done

TF1	001BH		Timer 1 Overﬂow

GSCTE	004BH		GSC Transmit Error

TI+RI	0023H		UART Transmit/Receive

Note that the locations of the basic 8051 interrupts are the same as in the rest of the MCS-51 Fam- ily. And relative to each other they retain the same positions in the polling sequence.

The locations of the new interrupts all follow the locations the basic 8051 interrupts in the Pro- gram Memory, but they are interleaved with them in the polling sequence.

To support the new interrupts a second Interrupt Enable register and A second Interrupt Priority register are implemented in the bit-addressable register space. The two Interrupt Enable registers in the 8XC152 are as follows:

IE:

7	6			5			4	3	2	1	0
EA							ES	ET1	EX1	ET0	EX0
EA							ES	ET1	EX1	ET0	EX0

Address of IE in SFR space = 0A8H (bit-addressable)

7				6			5	4	3	2	1	0
IEN1:							EGSTE	EDMA1	EGSTV	EDMA0	EGSRE	EGSRV

Address of IE1 in SFR space = 0C8H (bit-addressable)

The bits in the IE are unchanged from the standard 8051 IE register. The bits in IEN1 are as fol- lows:

EGSTE = 1 Enable GSC Transmit Error Interrupt

= 0 Disable

EDMA1 = 1 Enable DMA Channel 1 Done Interrupt

= 0 Disable

EGSTV = 1 Enable GSC Transmit Valid Interrupt

= 0 Disable

EDMA0 = 1 Enable DMA Channel 0 Done Interrupt

Kawasaki LSI USA, Inc.

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Kawasaki 80C152, KS152JB, 80C51 technical specifications Ti+Ri, ET1 EX1 ET0 EX0

Contents

Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate Function XTAL2 XTAL1RST Eben ALEPsen Epsen Special function Registers SFR map for the cpu Reset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon Pcon Port 0 I/O Pad Port 2 I/O Pad Port bit I/O Pads Ports 4,5 Comments ProgramPsen Epsen Fetch via TIMER/COUNTERS Tmod Timer/Counter Mode Control Register Tcon Timer/Counter Control Register Mode Timer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Pgsrv PX0EX0 Egsrv 2BH PT1 PDMA1EDMA1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Pcon Power Control Register Smod IDL Local Serial Channel Local Serial Port Mode Controller Serial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRC Csma Sdlc 11/IDLE External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter Tolerance Missing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive Tfifo DCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring Network Sdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Deﬁned Protocols Line Discipline Planning for Network Changes and Expansions DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver Interface Jitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit Waveforms Receiver Clock Recovery CSMA/CD Clock Recovery Rcbat Crce Determining Receiver ErrorsExternal Clocking Addressing Determining Line Discipline 2 CPU/DMA Control of the GSC Collisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and Receptions GMOD84H Xtclk PL1 PL0 PL1 PL0 Length Bits Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDL Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152 DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISA Serial Port Demand Mode External Demand Mode PCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal Memory DMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQ Internal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA Done Interrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 IPN1 GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPH Timer 0 LSB Timer Mode ControlGate Timer Timer 1 LSB Timer 0 MSB Timer 1 MSB Serial Data Buffer Serial Port ControlSM0 SBUF.7 Program Status Word RS1 RS0 Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2