Serial Port Control, SM0, Serial Data Buffer, Sbuf | Kawasaki 80C51

KS152JB Universal Communications Controller Technical Specifications

SERIAL PORT CONTROL

Bit:

7

6

5

4

3

2

1

0

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Mnemonic:

SCON

Address:

98h

SM0

Serial port, Mode 0 bit: The operation of SM0 is described below. .

SM1

Serial port Mode bit 1:

SM0

SM1 Mode

Description

Length

Baud rate

0

0

0

Synchronous

8

4/12 tclk

0

1

1

Asynchronous

10

variable

1

0

2

Asynchronous

11

64/32 tclk

1

1

3

Asynchronous

11

variable

SM2

Multiple MCU communication: Setting this bit to 1 enables the multiprocessor com-

munication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not

be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will

not be activated if a valid stop bit was not received.

REN

Receive enable: When set to 1 serial reception is enabled, else reception is disabled.

TB8

This is the 9th bit to be transmitted in modes 2 and 3. this bit is set and cleared by soft-

ware as desired.

RB8

In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the

stop bit that was received. In mode 0 it has no function.

TI

Transmit interrupt ﬂag: This ﬂag is set by hardware at the end of the 8th bit time in

mode 0, or at the beginning of the stop bit in all other modes during serial transmis-

sion. This bit must be cleared by software.

RI

Receive interrupt ﬂag: This ﬂag is set by hardware at the end of the 8th bit time in

mode 0, or halfway through the stop bits time in the other modes during serial recep-

tion. However the restrictions of SM2 applies on this bit. This bit can be cleared only

by software

The SCON sfr is set to 00h by a reset.

There is unrestricted read/write access to this SFR.

SERIAL DATA BUFFER

Bit:

7

6

5

4

3

2

1

0

SBUF.7

SBUF.6

SBUF.5

SBUF.4

SBUF.3

SBUF.2

SBUF.1

SBUF.0

Mnemonic:

SBUF

Address:

99h

SBUF.7-0 Serial data is read from or written to this location. It actually consists of two separate 8-bit registers. On is the receive resister, and the other is the transmit buffer. Any read access gets data from the receive data buffer, while write accesses are to the transmit data buffer.

Kawasaki LSI USA, Inc.

Page 116 of 120

Ver. 0.9 KS152JB2

Image 116

Kawasaki 80C51, KS152JB Serial Port Control, SM0, Serial Data Buffer, SBUF.7, SBUF.5 SBUF.4 SBUF.3, SBUF.1 SBUF.0, Sbuf

Contents

Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate Function RST XTAL1XTAL2 ALE PsenEben Epsen Special function Registers SFR map for the cpu Reset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod Pcon Port 0 I/O Pad Port 2 I/O Pad Port bit I/O Pads Ports 4,5 Program Psen EpsenComments Fetch via TIMER/COUNTERS Tmod Timer/Counter Mode Control Register Tcon Timer/Counter Control Register Mode Timer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv PX0 EX0Pgsrv Egsrv 2BH PDMA1 EDMA1PT1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Pcon Power Control Register Smod IDL Local Serial Channel Local Serial Port Mode Controller Serial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRC Csma Sdlc 11/IDLE External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter Tolerance Unexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing Tfifo Algorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring Network Using a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Deﬁned Protocols Line Discipline Planning for Network Changes and Expansions DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver Interface Jitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit Waveforms Receiver Clock Recovery CSMA/CD Clock Recovery Determining Receiver Errors External ClockingRcbat Crce Addressing Determining Line Discipline 2 CPU/DMA Control of the GSC Collisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and Receptions GMOD84H Xtclk PL1 PL0 PL1 PL0 Length Bits Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDL Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152 DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISA Serial Port Demand Mode External Demand Mode Timing Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory DMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode Using the HOLD/HLDA Acknowledge ARB REQ Dmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA Done Interrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 IPN1 GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPH Timer Mode Control Gate TimerTimer 0 LSB Timer 1 LSB Timer 0 MSB Timer 1 MSB Serial Port Control SM0Serial Data Buffer SBUF.7 Program Status Word RS1 RS0 Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2