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Kawasaki 80C152, KS152JB, 80C51 technical specifications Serial Port Mode

Models: 80C51 KS152JB 80C152

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KS152JB Universal Communications Controller Technical Specifications

Timer 1
Overﬂow
						Transmit Shift Register
2					1	STOP	SOUT	TxD
					1	STOP	SOUT	TxD
				Internal		PARIN
SMOD			Data Bus		0	START
0	1	Write to				LOAD
		SBUF				LOAD
		SBUF				CLOCK
						CLOCK
			TX START	TX SHIFT
		16	TX CLOCK	TI
			SERIAL				Serial Interrupt
			CONTROLLER
		16	RX CLOCK	RI
			RX CLOCK	LOAD
				SBUF
		1-TO-0	RX	RX SHIFT
		DETECTOR	START	RX SHIFT
		DETECTOR	START
						CLOCK		Internal
						PAROUT	SBUF	Internal
						PAROUT	SBUF	Data Bus
	RxD		BIT			SIN		Data Bus
			BIT
			DETECTOR
			DETECTOR			D8	RB8
						D8	RB8	Read
								Read
					Receive Shift Register			SBUF

Serial Port Mode 1

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously moni- tors the RxD line sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 counter.

The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejection feature of the serial port. If the ﬁrst bit detected after the falling edge of RxD pin, is not 0, then it indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF.

After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is set. However certain conditions must be met before, The loading and setting of RI can be done.

1.RI must be 0 and

2.Either SM2 = 0, or the received stop bit = 1.

Kawasaki LSI USA, Inc.

Page 25 of 120

Ver. 0.9 KS152JB2

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Kawasaki 80C152, KS152JB, 80C51 technical specifications Serial Port Mode

Contents

Introduction Technical Specifications PIN Description Pin DescriptionName Description Port Pin Name Alternate FunctionXTAL2 XTAL1RST Psen ALEEben EpsenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Scon ConfigurationsSbuf Indeterminate Tmod PconPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Psen Epsen ProgramComments Fetch viaTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEX0 PX0Pgsrv Egsrv 2BHEDMA1 PDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Manchester Encoding BIT Time CSMA/CD Data EncodingCollision Detection Jitter ToleranceMissing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition GSC Inactive Resolution of CollisionsResponse to a Detected Collision What the GSC was doing TfifoDCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Point-to-point Network PRIMARY/SECONDARY StationsMulti-Drop Network Ring NetworkHDLC/SDLC Comparison Using a Preamble in SdlcSdlc Hdlc User Deﬁned ProtocolsPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Receive Sampling Rate Received Local Value Manchester Encoding BIT TimeBIT Time Received Transmit WaveformsCSMA/CD Clock Recovery Receiver Clock RecoveryExternal Clocking Determining Receiver ErrorsRcbat Crce Addressing2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers Burst Mode Alternate Cycle ModeDAS IDA SAS ISAExternal Demand Mode Serial Port Demand Mode12 OSC.PERIODS ALE Psen P1 Inst Float Timing DiagramsPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal MemoryDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA AcknowledgeInternal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Stack Pointer PortData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Data Pointer High Timer ControlDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHGate Timer Timer Mode ControlTimer 0 LSB Timer 1 LSBTimer 1 MSB Timer 0 MSBSM0 Serial Port ControlSerial Data Buffer SBUF.7RS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2