Data Pointer High, Dph, Timer Control, TF1 | Kawasaki 80C51, 80C152

KS152JB Universal Communications Controller Technical Specifications

DATA POINTER HIGH
Bit:	7	6		5	4	3	2	1		0

	DPH.7		DPH.6	DPH.5	DPH.4	DPH.3	DPH.2	DPH.1	DPH.0

Mnemonic:		DPH						Address:		83h

This is the high byte of the 16-bit data pointer.

The DPH is reset to 00h by a reset.

There is unrestricted read/write access to this SFR.

TIMER CONTROL

Bit:

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Mnemonic:

TCON

Address: 88h

TF1

Timer 1 overﬂow ﬂag: This bit is set when Timer 1 overﬂows. It is cleared automati-

cally when the program does a timer 1 interrupt service routine. Software can also set

or clear this bit.

TR1

Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or

off.

TF0

Timer 0 overﬂow ﬂag: This bit is set when Timer 0 overﬂows. It is cleared automati-

cally when the program does a timer 0 interrupt service routine. Software can also set

or clear this bit.

TR0

Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or

off.

IE1

Interrupt 1 edge detect: Set by hardware when an edge/level is detected on

This

INT1.

bit is cleared by hardware when the service routine is vectored to only if the interrupt

was edge triggered. Otherwise it follows the pin.

IT1

Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level trig-

gered external inputs.

IE0

Interrupt 0 edge detect: Set by hardware when an edge/level is detected on

This

INT0.

bit is cleared by hardware when the service routine is vectored to only if the interrupt

was edge triggered. Otherwise it follows the pin.

IT0

Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level trig-

gered external inputs.

The TCON is reset to 00h by a reset.

There is unrestricted read/write access to this SFR.

Kawasaki LSI USA, Inc.

Page 113 of 120

Ver. 0.9 KS152JB2

Image 113

Kawasaki 80C51, KS152JB, 80C152 Data Pointer High, DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0, Dph, Timer Control, TF1

Contents

Introduction Technical Specifications PIN Description Pin DescriptionName Description Port Pin Name Alternate Function RST XTAL1XTAL2 Psen ALEEben Epsen SFR map for the cpu Special function Registers Reset Timing Reset Values of the SFRs Scon ConfigurationsSbuf Indeterminate Tmod Pcon Port bit I/O Pads Port 0 I/O Pad Port 2 I/O Pad Ports 4,5 Psen Epsen ProgramComments Fetch via Tmod Timer/Counter Mode Control Register TIMER/COUNTERS Mode Tcon Timer/Counter Control Register Timer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre Egsrv EX0 PX0Pgsrv Egsrv 2BH EDMA1 PDMA1PT1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Smod IDL Pcon Power Control Register Local Serial Channel Controller Local Serial Port Mode Serial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Introduction Global Serial Channel DC JAM CRC 11/IDLE CRC None 11/IDLE Csma Sdlc External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Manchester Encoding BIT Time CSMA/CD Data EncodingCollision Detection Jitter Tolerance Unexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition GSC Inactive Resolution of CollisionsResponse to a Detected Collision What the GSC was doing Tfifo Algorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Point-to-point Network PRIMARY/SECONDARY StationsMulti-Drop Network Ring Network HDLC/SDLC Comparison Using a Preamble in SdlcSdlc Hdlc User Deﬁned Protocols Planning for Network Changes and Expansions Line Discipline DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test Modes Jitter Receive Receive Sampling Rate Received Local Value Manchester Encoding BIT TimeBIT Time Received Transmit Waveforms CSMA/CD Clock Recovery Receiver Clock Recovery External Clocking Determining Receiver ErrorsRcbat Crce Addressing 2 CPU/DMA Control of the GSC Determining Line Discipline Collisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register Descriptions PL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0 Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA Operation DMA Registers Burst Mode Alternate Cycle ModeDAS IDA SAS ISA External Demand Mode Serial Port Demand Mode 12 OSC.PERIODS ALE Psen P1 Inst Float Timing DiagramsPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory DMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode ARB REQ Using the HOLD/HLDA Acknowledge Dmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control Bits Interrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RI IPN1 PT1 PX1 PT0 PX0 Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error Conditions GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Stack Pointer PortData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Data Pointer High Timer ControlDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPH Gate Timer Timer Mode ControlTimer 0 LSB Timer 1 LSB Timer 1 MSB Timer 0 MSB SM0 Serial Port ControlSerial Data Buffer SBUF.7 RS1 RS0 Program Status Word ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Accumulator Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2