Glossary | Kawasaki 80C51, KS152JB, 80C152 specs

KS152JB Universal Communications Controller Technical Specifications

RDN from being set.

CRCE

AE

RCABT

OVR

GREN

EOF RECEIVED

GSCRE

Clear

GREN

Set

RDN

Receive Error Flag (Logic for Clearing GREN, Setting RDN)

A CRC Error means the CRC generator did not come to its correct value after calculating the CRC of the message plus received CRC. An alignment error means the number of bits received between the BOF and EOF was not a multiple of 8.

In SDLC mode, the CRC bit gets set at the end of any frame in which there is a CRC error, and the AE bit gets set at the end of any frame in which there is an Alignment Error.

In CSMA/CD mode, if there is no CRC Error, neither CRCE nor AE will get set. If there is a CRC error and no Alignment Error, the CRCE bit will get set, but not the AE bit. If there is both a CRC Error and an Alignment Error, then the AE bit will get set, but not the CRCE bit. Thus in CSMA/ CD mode, the CRCE and AE bits are mutually exclusive.

The Receive Abort ﬂag, RCABT, gets set if an incoming frame was interrupted after received data had already passed to the Receive FIFO. In the SDLC mode, this can happen if a line idle condi- tion is detected before an EOF ﬂag is. In CSMA/CD mode, this can happen if there is a collision. In either case, the CPU will have to re-initialize whatever pointers and counters it might have been using.

The Overrun Error ﬂag, OVR, gets set if the GSC Receiver is ready to push a newly received byte onto the Receive FIFO, but the FIFO is full.

Up to 7 “dribble bits” can be received after the EOF without causing an error condition.

6.0 GLOSSARY

ADR0,1,2,3 (95H, 0A5H, 0B5H, 0C5H) - Address Match Registers 0, 1, 2, 3 - The contents of these SFR’s are compared against the address bits from the serial data on the GSC. If the address matches the SFR, then the C152 accepts that frame. If in 8 bit addressing mode a match with any of the four registers will trigger acceptance. In the 16 bit addressing mode, a match with ADR1:ADR0 or ADR3:ADR2 will be accepted. Address length is determined by GMOD (AL).

AE - Alignment Error, see RSTAT.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Kawasaki 80C51, KS152JB, 80C152 technical specifications Glossary

Contents

Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate Function RST XTAL1XTAL2 Eben ALEPsen Epsen Special function Registers SFR map for the cpu Reset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon Pcon Port 0 I/O Pad Port 2 I/O Pad Port bit I/O Pads Ports 4,5 Comments ProgramPsen Epsen Fetch via TIMER/COUNTERS Tmod Timer/Counter Mode Control Register Tcon Timer/Counter Control Register Mode Timer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Pgsrv PX0EX0 Egsrv 2BH PT1 PDMA1EDMA1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Pcon Power Control Register Smod IDL Local Serial Channel Local Serial Port Mode Controller Serial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRC Csma Sdlc 11/IDLE External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter Tolerance Unexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive Tfifo Algorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring Network Sdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Deﬁned Protocols Line Discipline Planning for Network Changes and Expansions DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver Interface Jitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit Waveforms Receiver Clock Recovery CSMA/CD Clock Recovery Rcbat Crce Determining Receiver ErrorsExternal Clocking Addressing Determining Line Discipline 2 CPU/DMA Control of the GSC Collisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and Receptions GMOD84H Xtclk PL1 PL0 PL1 PL0 Length Bits Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDL Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152 DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISA Serial Port Demand Mode External Demand Mode PCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal Memory DMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode Using the HOLD/HLDA Acknowledge ARB REQ Dmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA Done Interrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 IPN1 GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPH Timer 0 LSB Timer Mode ControlGate Timer Timer 1 LSB Timer 0 MSB Timer 1 MSB Serial Data Buffer Serial Port ControlSM0 SBUF.7 Program Status Word RS1 RS0 Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2