Local Serial Port Mode, Controller | Kawasaki KS152JB, 80C152, 80C51

KS152JB Universal Communications Controller Technical Specifications

				Transmit Shift Register
CLOCK					SOUT	RxD
			Internal	PARIN		P3.0 Alternate
			Internal	PARIN		Output function
		Data Bus
		Write to		LOAD
12	4	SBUF		LOAD
12	4	SBUF		CLOCK
	SM2	TX START	TX SHIFT
	SM2	TX CLOCK	TI
0	1	TX CLOCK	TI
0	1	SERIAL			Serial Interrupt
		SERIAL
		CONTROLLER
		CONTROLLER
			RI
		RX CLOCK	SHIFT			TxD
			CLOCK			TxD
			CLOCK			P3.1 Alternate
			LOAD			P3.1 Alternate
			LOAD			Output function
RI		RX	SBUF
		RX	RX SHIFT
REN		START	RX SHIFT
		START

				CLOCK		Internal
				PAROUT	SBUF	Internal
				PAROUT	SBUF	Data Bus
RxD				SIN
P3.0 Alternate
Input function						Read
				Receive Shift Register		SBUF

Local Serial Port Mode 0

MODE 1

In Mode 1, the full duplex mode is used. Serial communication frames are made up of 10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB ﬁrst), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this mode is variable.In this mode 10 bits are transmitted (on TxD) or received (on RxD). The frame consists of a start bit (0), 8 data bits (LSB ﬁrst), and a stop bit (1). On reception, the stop bit is placed into RB8. Tthe baud rate is determined by the Timer 1 or timer 2 overﬂow rate, and so it can be controlled by the user.

The ﬁgure below gives the simpliﬁed functional block for Mode 1.

Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin following the ﬁrst roll-over of divide by 16 counter. The next bit is placed on TxD pin following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 counter and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is transmitted. The TI ﬂag is set in the S1 state after the stop bit has been put out on TxD pin. This will be at the 10th rollover of the divide by 16 counter after a write to SBUF.

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Kawasaki KS152JB, 80C152, 80C51 technical specifications Local Serial Port Mode, Controller

Contents

Introduction Technical Specifications Pin Description PIN DescriptionName Description Port Pin Name Alternate Function XTAL1 XTAL2RST ALE PsenEben Epsen Special function Registers SFR map for the cpu Reset Timing Reset Values of the SFRs Configurations SconSbuf Indeterminate Tmod Pcon Port 0 I/O Pad Port 2 I/O Pad Port bit I/O Pads Ports 4,5 Program Psen EpsenComments Fetch via TIMER/COUNTERS Tmod Timer/Counter Mode Control Register Tcon Timer/Counter Control Register Mode Timer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv PX0 EX0Pgsrv Egsrv 2BH PDMA1 EDMA1PT1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Pcon Power Control Register Smod IDL Local Serial Channel Local Serial Port Mode Controller Serial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRC Csma Sdlc 11/IDLE External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space CSMA/CD Data Encoding Manchester Encoding BIT TimeCollision Detection Jitter Tolerance Narrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition Resolution of Collisions GSC InactiveResponse to a Detected Collision What the GSC was doing Tfifo Backoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement PRIMARY/SECONDARY Stations Point-to-point NetworkMulti-Drop Network Ring Network Using a Preamble in Sdlc HDLC/SDLC ComparisonSdlc Hdlc User Deﬁned Protocols Line Discipline Planning for Network Changes and Expansions DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver Interface Jitter Receive Local Value Manchester Encoding BIT Time Receive Sampling Rate ReceivedBIT Time Received Transmit Waveforms Receiver Clock Recovery CSMA/CD Clock Recovery Determining Receiver Errors External ClockingRcbat Crce Addressing Determining Line Discipline 2 CPU/DMA Control of the GSC Collisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and Receptions GMOD84H Xtclk PL1 PL0 PL1 PL0 Length Bits Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDL Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152 DMA Registers Alternate Cycle Mode Burst ModeDAS IDA SAS ISA Serial Port Demand Mode External Demand Mode Timing Diagrams 12 OSC.PERIODS ALE Psen P1 Inst FloatPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQ ALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA Done Interrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 IPN1 GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Port Stack PointerData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Timer Control Data Pointer HighDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPH Timer Mode Control Gate TimerTimer 0 LSB Timer 1 LSB Timer 0 MSB Timer 1 MSB Serial Port Control SM0Serial Data Buffer SBUF.7 Program Status Word RS1 RS0 Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2