IE0 | Kawasaki KS152JB, 80C152, 80C51 specs

KS152JB Universal Communications Controller Technical Specifications

As shown in Figure above, the Receive Valid interrupt can be signalled either by the RFNE ﬂag (Receive FIFO Not Empty), or by the RDN ﬂag (Receive Done). Which one of these ﬂags causes the interrupt depends on the setting of the DMA bit in the SFR named TSTAT.

DMA = 0 means the DMA hardware is not conﬁgured to service the GSC, so the CPU will service it in software in response to the Receive FIFO not being empty. In that case, RFNE generates the Receive Valid interrupt.

DMA = 1 means the DMA hardware is conﬁgured to service the GSC, in which case the CPU need not be interrupted till the receive is complete. In that case RDN generates the Receive Valid interrupt.

Similarly the Transmit Valid interrupt can be signalled either by the TFNF ﬂag (Transmit FIFO Not Full), or by the TDN ﬂag (Transmit Done), depending on whether the DMA bit is 0 or 1.

Note that setting the DMA bit does not itself conﬁgure the DMA channels to service the GSC. That job must be done by software writes to the DMA registers. the DMA bit only selects whether the GSCRV and GSCTV interrupts are ﬂagged by a FIFO needing service or by an “operation done” signal.

The Receive and Transmit Error interrupt ﬂags are generated by the logical OR of a number of error conditions, which are described in Section 3.6.5.

Each interrupt is assigned a ﬁxed location in Program Memory, and the interrupt causes the CPU to jump to that location. All the interrupt ﬂags are sampled at S5P2 of every machine cycle, and then the samples are sequentially polled during the next machine cycle. If more than one interrupt of same priority is active, the one that is highest in the polling sequence is serviced ﬁrst. The inter- rupts and their ﬁxed locations in Program Memory are listed below in the order of their polling sequence

		Table 14:

Interrupt	Location		Name


IE0	0003H		External Interrupt 0

GSCRV	002BH		GSC Receive Valid

TF0	000BH		Timer 0 Overﬂow

GSCRE	0033H		GSC Receive Error

DMA0	003BH		DMA channel 0 Done

IE1	0013H		External interrupt 1

GSCTV	0043H		GSC Transmit Valid

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Kawasaki KS152JB, 80C152, 80C51 technical specifications IE0

Contents

Introduction Technical Specifications PIN Description Pin DescriptionName Description Port Pin Name Alternate Function XTAL1 XTAL2RST Psen ALEEben Epsen SFR map for the cpu Special function Registers Reset Timing Reset Values of the SFRs Scon ConfigurationsSbuf Indeterminate Tmod Pcon Port bit I/O Pads Port 0 I/O Pad Port 2 I/O Pad Ports 4,5 Psen Epsen ProgramComments Fetch via Tmod Timer/Counter Mode Control Register TIMER/COUNTERS Mode Tcon Timer/Counter Control Register Timer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre Egsrv EX0 PX0Pgsrv Egsrv 2BH EDMA1 PDMA1PT1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Smod IDL Pcon Power Control Register Local Serial Channel Controller Local Serial Port Mode Serial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Introduction Global Serial Channel DC JAM CRC 11/IDLE CRC None 11/IDLE Csma Sdlc External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Manchester Encoding BIT Time CSMA/CD Data EncodingCollision Detection Jitter Tolerance Narrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition GSC Inactive Resolution of CollisionsResponse to a Detected Collision What the GSC was doing Tfifo Backoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement Point-to-point Network PRIMARY/SECONDARY StationsMulti-Drop Network Ring Network HDLC/SDLC Comparison Using a Preamble in SdlcSdlc Hdlc User Deﬁned Protocols Planning for Network Changes and Expansions Line Discipline DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test Modes Jitter Receive Receive Sampling Rate Received Local Value Manchester Encoding BIT TimeBIT Time Received Transmit Waveforms CSMA/CD Clock Recovery Receiver Clock Recovery External Clocking Determining Receiver ErrorsRcbat Crce Addressing 2 CPU/DMA Control of the GSC Determining Line Discipline Collisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register Descriptions PL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0 Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA Operation DMA Registers Burst Mode Alternate Cycle ModeDAS IDA SAS ISA External Demand Mode Serial Port Demand Mode 12 OSC.PERIODS ALE Psen P1 Inst Float Timing DiagramsPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA Acknowledge ALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control Bits Interrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RI IPN1 PT1 PX1 PT0 PX0 Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error Conditions GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Stack Pointer PortData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Data Pointer High Timer ControlDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPH Gate Timer Timer Mode ControlTimer 0 LSB Timer 1 LSB Timer 1 MSB Timer 0 MSB SM0 Serial Port ControlSerial Data Buffer SBUF.7 RS1 RS0 Program Status Word ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Accumulator Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2