Das Ida, Sas Isa, Alternate Cycle Mode | Kawasaki KS152JB, 80C152

KS152JB Universal Communications Controller Technical Specifications

DAS	IDA	Destination	Auto-Increment

0	0	External RAM	no
0	1	External RAM	yes
1	0	SFR	no
1	1	Internal RAM	yes

SAS	ISA	Source	Auto-Increment

0	0	External RAM	no
0	1	External RAM	yes
1	0	SFR	no
1	1	Internal RAM	yes

There are four modes in which the DMA channel can operate. These are selected by the bits DM and TM (Demand Mode and Transfer Mode) in DCONn:

DM	TM	Operating Mode

0	0	Alternate Cycles Mode
0	1	Burst Mode
1	0	Serial Port Demand Mode
1	1	External Demand Mode

The operating modes are described below.

4.1.1 ALTERNATE CYCLE MODE

In Alternate Cycles Mode the DMA is initiated by setting the GO bit in DCONn. Following the instruction that set the GO bit, one more instruction is executed, and then the ﬁrst data byte is transferred from the source address to the destination address. Then another instruction is exe- cuted, and then another byte of data is transferred, and so on in this manner.

Each time a data byte is transferred, BCRn (Byte Count Register for DMA Channel n) is decre- mented. When it reaches 0000H, on-chip hardware clears the GO bit and sets the DONE bit, and the DMA ceases. The DONE bit ﬂags an interrupt.

4.1.2 BURST MODE

Burst Mode differs from Alternate Cycles mode only in that once the data transfer has begun, pro- gram execution is entirely suspended until BCRn reaches 0000H, indicating that all data bytes that were to be transferred have been transferred. The interrupt control hardware remains active

Kawasaki LSI USA, Inc.

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Ver. 0.9 KS152JB2

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Kawasaki KS152JB, 80C152, 80C51 technical specifications Das Ida, Sas Isa, Alternate Cycle Mode, Burst Mode

Contents

Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate Function XTAL1 XTAL2RST Eben ALEPsen Epsen Special function Registers SFR map for the cpu Reset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon Pcon Port 0 I/O Pad Port 2 I/O Pad Port bit I/O Pads Ports 4,5 Comments ProgramPsen Epsen Fetch via TIMER/COUNTERS Tmod Timer/Counter Mode Control Register Tcon Timer/Counter Control Register Mode Timer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Pgsrv PX0EX0 Egsrv 2BH PT1 PDMA1EDMA1 ET1 1BH Kawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Pcon Power Control Register Smod IDL Local Serial Channel Local Serial Port Mode Controller Serial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Global Serial Channel Introduction 11/IDLE CRC None DC JAM CRC Csma Sdlc 11/IDLE External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter Tolerance Narrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive Tfifo Backoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring Network Sdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Deﬁned Protocols Line Discipline Planning for Network Changes and Expansions DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver Interface Jitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit Waveforms Receiver Clock Recovery CSMA/CD Clock Recovery Rcbat Crce Determining Receiver ErrorsExternal Clocking Addressing Determining Line Discipline 2 CPU/DMA Control of the GSC Collisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and Receptions GMOD84H Xtclk PL1 PL0 PL1 PL0 Length Bits Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDL Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152 DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISA Serial Port Demand Mode External Demand Mode PCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal Memory 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge Using the HOLD/HLDA Acknowledge ARB REQ ALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA Done Interrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0 IPN1 GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPH Timer 0 LSB Timer Mode ControlGate Timer Timer 1 LSB Timer 0 MSB Timer 1 MSB Serial Data Buffer Serial Port ControlSM0 SBUF.7 Program Status Word RS1 RS0 Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2