KS152JB Universal Communications Controller Technical Specifications
2.11 SINGLE-STEP OPERATION
The processor does not have any pin which can directly force it to operate in the single-step mode. However the user can use the interrupt structure to obtain single-step operation. The user will be aware that the processor executes one more instruction after a RETI instruction and only then does it respond to an interrupt request. Thus once an interrupt routine has begun, it cannot enter another routine unless one instruction of the interrupted program has been executed. The external interrupts can be used to good effect to achieve this. One of the interrupts, say INT0 is pro- grammed to be level activated interrupt. Now when the processor detects a low on this pin, it will vector to the interrupt service routine. The interrupt service routine will have a simple loop which will wait till the INT0 pin is pulsed, high to low. The processor will now return to the interrupted program and execute at least one instruction. If the INT0 pin is held low, then another interrupt request is generated and the interrupt service routine is again executed.
| | | | |
JNB | P3.2, $ | ; wait here till INT0 goes high |
JB | P3.2, $ | ; wait here till | INT0 | goes low |
RETI | | ; return to the interrupted program and execute at least one more |
| | ; instruction |
In this way a single instruction of the main program will be executed every time INT0 is pulsed.
Kawasaki LSI USA, Inc. | Page 30 of 120 | Ver. 0.9 KS152JB2 |
