Timer 0 MSB, Timer 1 MSB | Kawasaki 80C152, KS152JB, 80C51 manual

KS152JB Universal Communications Controller Technical Specifications

TL1.7-0 Timer 1 LSB

The TL1 sfr is set to 00h on any reset.

There is unrestricted read/write access to this SFR.

TIMER 0 MSB

Bit:

7

6

5

4

3

2

1

0

TH0.7

TH0.6

TH0.5

TH0.4

TH0.3

TH0.2

TH0.1

TH0.0

Mnemonic:

TH0

Address:

8Ch

TH0.7-0

Timer 0 MSB

The TH0 sfr is set to 00h on any reset.

There is unrestricted read/write access to this SFR.

TIMER 1 MSB

Bit:

7

6

5

4

3

2

1

0

TH1.7

TH1.6

TH1.5

TH1.4

TH1.3

TH1.2

TH1.1

TH1.0

Mnemonic:

TH1

Address:

8Dh

TH1.7-0

Timer 1 MSB

The TH1 sfr is set to 00h on any reset.

There is unrestricted read/write access to this SFR.

PORT 1

Bit:

7

6

5

4

3

2

1

0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

Mnemonic:

P1

Address:

90h

P1.7-0 General purpose I/O port. Most instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, the port latch is read.

The P1 sfr is set to FFh by a reset.

There is unrestricted read/write access to this SFR.

Kawasaki LSI USA, Inc.

Page 115 of 120

Ver. 0.9 KS152JB2

Image 115

Kawasaki 80C152, KS152JB, 80C51 technical specifications Timer 0 MSB, Timer 1 MSB

Contents

Introduction Technical Specifications Pin Name Alternate Function Pin DescriptionPIN Description Name Description Port XTAL2 XTAL1RST Epsen ALEPsen Eben SFR map for the cpu Special function Registers Reset Timing Reset Values of the SFRs Pcon ConfigurationsScon Sbuf Indeterminate Tmod Port bit I/O Pads Port 0 I/O Pad Port 2 I/O Pad Ports 4,5 Fetch via ProgramPsen Epsen Comments Tmod Timer/Counter Mode Control Register TIMER/COUNTERS Mode Tcon Timer/Counter Control Register Timer/Counter in Mode IE Interrupt Enable Register Timer/Counter 0 in ModeInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre Egsrv Egsrv 2BH PX0EX0 Pgsrv ET1 1BH PDMA1EDMA1 PT1 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Status of the External Pins during Idle and Power Down Power Down and IdleALE Psen Smod IDL Pcon Power Control Register Local Serial Channel Controller Local Serial Port Mode Serial Port Mode Mode Load Sbuf Baud Rates Smod Timer 1 generated commonly used Baud ratesMHZ JNB SINGLE-STEP OperationReti Kawasaki LSI USA Inc Introduction Global Serial Channel DC JAM CRC 11/IDLE CRC None 11/IDLE Csma Sdlc External clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Frame Format CSMA/CD OverviewPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Jitter Tolerance CSMA/CD Data EncodingManchester Encoding BIT Time Collision Detection Missing 0-to-1 Transition Narrow PulsesUnexpected 1-to-0 Transition Tfifo Resolution of CollisionsGSC Inactive Response to a Detected Collision What the GSC was doing DCR BackoffAlgorithm Prbs Tcdcnt Load Bkoff Slot Clock Myslot Random BackoffBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 Nrzi BIT Time Data EncodingBIT STUFFING/STRIPPING Line Idle Sending Abort CharacterAcknowledgement Ring Network PRIMARY/SECONDARY StationsPoint-to-point Network Multi-Drop Network User Deﬁned Protocols Using a Preamble in SdlcHDLC/SDLC Comparison Sdlc Hdlc Planning for Network Changes and Expansions Line Discipline DMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test Modes Jitter Receive Transmit Waveforms Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received BIT Time Received CSMA/CD Clock Recovery Receiver Clock Recovery Addressing Determining Receiver ErrorsExternal Clocking Rcbat Crce 2 CPU/DMA Control of the GSC Determining Line Discipline Collisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register Descriptions PL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0 Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA Operation DMA Registers SAS ISA Alternate Cycle ModeBurst Mode DAS IDA External Demand Mode Serial Port Demand Mode DMA Transfer from Internal Memory to Internal Memory Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float PCH P2 SFR DMA Cycle Resume Program Execution DMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle Resume Program Execution Arbiter Mode Request ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA Acknowledge Internal Logic of the Arbiter ALE ARB If Hlda = ALE AEQ ALE REQDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control Bits Interrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RI IPN1 PT1 PX1 PT0 PX0 Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error Conditions GSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8 Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 PortStack Pointer Data Pointer LOW DPH Timer ControlData Pointer High DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer 1 LSB Timer Mode ControlGate Timer Timer 0 LSB Timer 1 MSB Timer 0 MSB SBUF.7 Serial Port ControlSM0 Serial Data Buffer RS1 RS0 Program Status Word ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Accumulator Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2