Sun Microsystems CP3260 manual Cores, 5.2.1.3 L2 Cache, Memory Controller, 5.2.1.5 I/O Interface

5.2.1.2Cores

The UltraSPARC T2 processor provides 8 physical SPARC processor cores and each physical core is capable of supporting 8 threads for a total of 64 threads.

5.2.1.3L2 Cache

The UltraSPARC T2 provides a total of 4 Mbytes of L2 cache banked 8 ways.

5.2.1.4Memory Controller

The UltraSPARC T2 supports 4 FB-DIMM memory controllers, each controller capable of supporting 2 FB-DIMM memory channels. The UltraSPARC T2 connects directly to 8 DIMMS (one DIMM per channel) providing for a total of 8 DIMM slots.

See Section 5.2.2, “Memory Subsystem” on page 5-9 for details on the Netra CP3260 memory design.

5.2.1.5I/O Interface

The UltraSPARC T2 provides the following I/O interfaces

■x8 PCI Express interface

■Two 10 Gbps Ethernet (XAUI) ports

PCI Express

The UltraSPARC T2 provides a PCI Express Unit (PEU) that implements the root complex behavior of the PCI -Express Base specification 1.0A.

The PEU supports x1, x2, x4, and x8 configuration at the data rate of 2.5Bb/s in each direction. The PEU also supports the lane reversal feature thus easing blade server routing restrictions.

XAUI Interface

The XAUI interface is a high speed point-to-point serial interface with four differential pairs for transmit (TX) and four differential pairs for receive (RX), operating at 3.125 Gbps.

5-8Netra CP3260 Blade Server User’s Guide • April 2009