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Texas Instruments MSP50C614 Manual

414 pages1.78 Mb

Preface
3Read This First
- About This Manual
- How to Use This Manual
- Notational Conventions
  - value
  - [, ... , value
  - ]
- 5Information About Cautions and Warnings
- Trademarks
7Contents
12Figures
14Tables
16Notes, Cautions, and Warnings
17Introduction to the MSP50C614
- Chapter 1
  - 181.1 Features of the C614
  - 191.2 Applications
  - 201.3 Development Device: MSP50P614
  - 211.4 Functional Description
  - 221.5 C605 and C604 (Preliminary Information)
    - 1-7
    - 23Figure 11. Functional Block Diagram for the C614
      - 1-8
    - 24Figure 12. Oscillator and PLL Connection
      - a) Crystal Oscillator Operation Connections
      - b) Resistor Trim Operation Connections
        1-9
    - 25Figure 13. RESET Circuit
      - 1-10
  - 261.6 Terminal Assignments and Signal Descriptions
    - Application Circuits
    - Scan Port Bond Out
    - Comparator
    - Table 11. Signal and Pad Descriptions for the C614
    - 27Table 12. MSP50C614 100-Pin PJM Plastic Package Pinout Description
    - 28Figure 14. MSP50C614 100 Pin PJM PLastic Package Pinout (Preliminary Information)
      - 1-13
    - 29Figure 15. 120 Pin Grid Array Package for the Development Device, P614
31MSP50C614 Architecture
- Chapter 2
  - 322.1 Architecture Overview
    - 2-3
    - 33Figure 21. MSP50C614 Core Processor Block Diagram
      - Indicates internal programmable registers.
      - 342-4
  - 352.2 Computation Unit
    - 2.2.1 Multiplier
    - Table 21. Signed and Unsigned Integer Representation
    - 37Figure 23. Overview of the Multiplier Unit Operation
      - 2.2.2 Arithmetic Logic Unit
        38Multiplier
        2.2.2.1 Accumulator Block
    - 39Figure 24. Overview of the Arithmetic Logic Unit
      - 2.2.2.2 Accumulator Pointer Block
    - 40Figure 25. Overview of the Arithmetic Logic Unit
      - 2.2.2.3 String Operations
  - 412.3 Data Memory Address Unit
    - 42Figure 26. Data Memory Address Unit
      - 2.3.1 RAM Configuration
        Multiplier
      - 432.3.2 Data Memory Addressing Modes
  - 442.4 Program Counter Unit
    - Data Memory Address Unit
  - 2.5 Bit Logic Unit
  - 452.6 Memory Organization: RAM and ROM
    - 2.6.1 Memory Map
      - Peripheral Communications (Ports)
        Memory Organization: RAM and ROM
        
        2-16
    - 46Figure 27. C614 Memory Map (not drawn to scale)
      - 2.6.2 Peripheral Communications (Ports)
        ).
        DAC Control and Data Registers
    - 47Table 22. Summary of C614s Peripheral Communications Ports
    - 48Table 22. Summary of C614s Peripheral Communications Ports (Continued)
      - 2.6.3 Interrupt Vectors
        ROM Code Security
      - 492.6.4 ROM Code Security
      - 2.6.5 Macro Call Vectors
        VCALL
  - 522.7 Interrupt Logic
    - 53Internal and External Interrupts
    - Interrupt/General Control Register
    - Peripheral Communications (Ports)
    - 54 Inter- rupt Vectors
      - Interrupt Logic
        2-25
    - 55Figure 28. Interrupt Initialization Sequence
  - 562.8 Timer Registers
    - 57Clock Speed Control Register
    - Clock Control
    - 58Interrupt/General Control Register
  - 592.9 Clock Control
    - 2.9.1 Oscillator Options
      - Clock Speed Con- trol Register
    - 2.9.2 PLL Performance
    - 60Figure 29. PLL Performance
      - 2.9.3 Clock Speed Control Register
        61MSP50C614 Electrical Specifications
      - 622.9.4 RTO Oscillator Trim Adjustment
  - 632.10 Execution Timing
    - Figure 210. Instruction Execution and Timing
  - 642.11 Reduced Power Modes
    - MSP50C614 Electrical Specifications
    - 66greater
    - DAC Control and Data Registers
      - Reduced Power Modes
    - 67Table 23. Programmable Bits Needed to Control Reduced Power Modes
    - 68Table 24. Status of Circuitry When in Reduced Power Modes (Refer to Table 23)
      - greater
    - 69Table 25. How to Wake-Up from Reduced Power Modes (Refer to Table 23 and Table 24)
      - Comparator
      - I/O
    - 70Table 26. Destination of Program Counter on Wake-Up Under Various Conditions
71Peripheral Functions
- Chapter 3
  - 723.1 I/O
    - 3.1.1 General-Purpose I/O Ports
      - 73Branch on D Port
      - Comparator
    - 743.1.2 Dedicated Input Port F
    - 753.1.3 Dedicated Output Port G
    - 763.1.4 Branch on D Port
    - 3.1.5 Internal and External Interrupts
      - DAC Control and Data
      - Registers
      - Timer Registers
      - Reduced Power Modes
    - 77Table 31. Interrupts
  - 783.2 Digital-to-Analog Converter (DAC)
    - 3.2.1 Pulse-Density Modulation Rate
      - PDM Clock Divider
      - optional
      - MSP50C614 Electrical Specifications
      - Clock Speed Control Register
    - 3.2.2 DAC Control and Data Registers
      - 79C5x
      - style
      - C5x style
      - wrap-around
    - 3.2.3 PDM Clock Divider
    - 80Figure 31. PDM Clock Divider
      - 82Digital-to-Analog Converter (DAC)
      - 3-12
      - 83Digital-to-Analog Converter (DAC)
        3-13
      - Peripheral Functions
  - 843.3 Comparator
    - transition
    - falling
    - starts
    - 85Figure 32. Relationship Between Comparator/Interrupt Activity and the TIMER1 Control
  - 873.4 Interrupt/General Control Register
    - stops
    - starts
  - 893.5 Hardware Initialization States
    - Application Circuits
    - not
    - MSP50C614 Electrical Specifications
    - every
    - after
    - 90partially
93Assembly Language Instructions
- Chapter 4
  - 944.1 Introduction
  - 4.2 System Registers
    - 4.2.1 Multiplier Register (MR)
    - 4.2.2 Shift Value Register (SV)
    - 4.2.3 Data Pointer Register (DP)
    - 4.2.4 Program Counter (PC)
    - 4.2.5 Top of Stack, (TOS)
    - 95Figure 41. Top of Stack (TOS) Register Operation
      - 964.2.6 Product High Register (PH)
      - 4.2.7 Product Low Register (PL)
      - 4.2.8 Accumulators (AC0AC31)
      - 974.2.9 Accumulator Pointers (AP0AP3)
      - 4.2.10 Indirect Register (R0R7)
        n+2
        n
      - 984.2.11 String Register (STR)
      - 4.2.12 Status Register (STAT)
        System Registers
    - 99Table 41. Status Register (STAT)
  - 1004.3 Instruction Syntax and Addressing Modes
    - 4.3.1 MSP50P614/MSP50C614 Instruction Syntax
    - 4.3.2 Addressing Modes
      - indirect with post modification
      - am
    - 101Table 42. Addressing Mode Encoding
    - 102Table 43. Rx Bit Description
    - Table 44. Addressing Mode Bits and {adrs} Field Description
      - Instruction Syntax and Addressing Modes
        4-11
    - 103Table 45. MSP50P614/MSP50C614 Addressing Modes Summary
      - Operation Syntax
    - Table 46. Auto Increment and Auto Decrement Modes
      - No modification 0 0 Aufto increment ++A 0 1 Auto decrement A 1 0 String mode 1 1
      - ] have either a A or a ++A in the instruction. See Table 46.
    - 104Table 47. Flag Addressing Field {flagadrs} for Certain Flag Instructions (Class 8a)
      - 4.3.3 Immediate Addressing
        imm
        name dest
    - 105Table 48. Initial Processor State for the Examples Before Execution of Instruction
      - 1064.3.4 Direct Addressing
        dma16
        
        src
        dma16
        
        name
      - 4.3.5 Indirect Addressing
    - 107Table 49. Indirect Addressing Syntax
      - 1084.3.6 Relative Addressing
        1094.3.6.2 Short Relative
        offset7
      - 4.3.7 Flag Addressing
    - 111Figure 42. Relative Flag Addressing
      - dma6
      - offset6
      - 1124.3.8 Tag/Flag Bits
  - 1144.4 Instruction Classification
    - Table 410. Symbols and Explanation
      - Instruction Classification
    - 115Table 411. Symbols and Explanation (Continued)
    - Table 411. Instruction Classification
    - 116Table 411. Instruction Classification (Continued)
    - 117Table 412. Classes and Opcode Definition
      - 4.4.1 Class 1 Instructions: Memory and Accumulator Reference
      - s
      - adrs
      - pm
      - am
        Instruction Classification
        
        4-26
        s
        Class 1b 0 1 C1b
        field (A
    - 118Table 413. Class 1 Instruction Encoding
      - Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 1a 0 0 C1a ~A~
      - n adrs
    - Table 414. Class 1a Instruction Description
    - 119Table 415. Class 1b Instruction Description
    - 120Table 415. Class 1b Instruction Description (Continued)
      - 4.4.2 Class 2 Instructions: Accumulator and Constant Reference
    - 121Table 416. Class 2 Instruction Encoding
    - Table 417. Class 2a Instruction Description
    - 122Table 418. Class 2b Instruction Description
      - 4.4.3 Class 3 Instruction: Accumulator Reference
    - 123Table 419. Class 3 Instruction Encoding
    - Table 420. Class 3 Instruction Description
      - 4.4.4 Class 4 Instructions: Address Register and Memory Reference
    - 126Table 421. Class 4a Instruction Encoding
    - 127Table 422. Class 4a Instruction Description
    - Table 423. Class 4b Instruction Description
    - Table 424. Class 4c Instruction Description
    - Table 425. Class 4d Instruction Description
      - 4.4.5 Class 5 Instructions: Memory Reference
    - 128Table 426. Class 5 Instruction Encoding
    - Table 427. Class 5 Instruction Description
    - 130Table 427. Class 5 Instruction Description (Continued)
      - 4.4.6 Class 6 Instructions: Port and Memory Reference
    - Table 428. Class 6a Instruction Encoding
    - Table 429. Class 6a Instruction Description
    - 131Table 430. Class 6b Instruction Description
      - 4.4.7 Class 7 Instructions: Program Control
        Not
    - 132Table 431. Class 7 Instruction Encoding and Description
    - 133Table 431. Class 7 Instruction Encoding and Description (Continued)
      - 4.4.8 Class 8 Instructions: Logic and Bit
    - Table 432. Class 8a Instruction Encoding
    - 134Table 433. Class 8a Instruction Description
    - Table 434. Class 8b Instruction Description
      - 4.4.9 Class 9 Instructions: Miscellaneous
    - 135Table 435. Class 9a Instruction Encoding
    - Table 436. Class 9a Instruction Description
    - Table 437. Class 9b Instruction Description
    - Table 438. Class 9c Instruction Description
    - Table 439. Class 9d Instruction Description
  - 1364.5 Bit, Byte, Word and String Addressing
  - 1414.6 MSP50P614/MSP50C614 Computational Modes
    - 142Table 441. MSP50P614/MSP50C614 Computational Modes
  - 1454.7 Hardware Loop Instructions
    - equal to zero
    - a
    - 146Table 442. Hardware Loops in MSP50P614/MSP50C614
  - 1474.8 String Instructions
    - Table 443. Initial Processor State for String Instructions
      - 148can
  - 1494.9 Lookup Instructions
    - Table 444. Lookup Instructions
  - 1514.10 Input/Output Instructions
  - 4.11 Special Filter Instructions
    - k-N
    - k-
    - y
    - Figure 45. FIR Filter Structure
      - 153The second to last RAM location in the circular buffer is tagged
      - backwards
      - 155wrap around
      - Wrap around
    - 159Figure 46. Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps
      - Special Filter Instructions
    - 160Figure 47. Filter Instruction and Circular Buffering for N+1 Tap Filter
      - m
      - sample_buf
      - Conditionals
  - 1614.12 Conditionals
  - 1624.13 Legend
    - All instructions of the MSP50P614/MSP50C614 use the following syntax:
    - italics
    - , mod
    - , src1
    - , src
    - name
      - type means it is a variable. [ ] square brackets enclose optional arguments. Operands
    - 165Table 445. Auto Increment and Decrement
    - Table 446. Addressing Mode Bits and adrs Field Description
    - Table 447. Flag Addressing Syntax and BIts
  - 1664.14 Individual Instruction Descriptions
    - 1674.14.1 ADD Add word
      - mod
      - is R
      - is A
      - PC PC +
      - +
      - +
      - Execution [premodify AP if
        imm5
        src1
        src
        dest
        label
      - specified]
      - : RCF, RZF are set accordingly src1 is {
      - }: TAG is set accordingly
    - 1694.14.2 ADDB ADD BYTE
    - 1704.14.3 ADDS Add String
      - string +
      - string to the value of
      - Description Add value of
      - src1 is {
      - is A
      - string
      - string PC PC +
      - }: TAG is set accordingly
      - string and store resulting string in
    - 1724.14.4 AND Bitwise AND
      - Execution [premodify AP if
      - is {
      - is TF
      - is A
      - PC PC +
      - AND
      - AND
      - specified]
      - bits in STAT register are set accordingly
      - Description
    - 1744.14.5 ANDB Bitwise AND Byte
    - 1754.14.6 ANDS Bitwise AND String
    - 1764.14.7 BEGLOOP Begin Loop
      - mask interrupts
    - 1774.14.8 CALL Unconditional Subroutine Call
    - 1784.14.9 C
    - Conditional Subroutine Call
      - Execution IF (
      - = true) *R7 TOS TOS PC + 2 PC
      - pma16
        R7 R7 + 2 ELSE NOP PC PC + 2 Flags Affected none
        4-87
    - 179Table 448. Names for cc
      - 180Description If
      - 4-90
      - 1824.14.10 CMP Compare Two Words
        ,
        , C
        (i.e.,
        from
        Description Subtract value of
        {adrs}
        is
        is R
        is A
        src src1
        Execution [premodify AP if
        next A
        [,
        next A
        ~ [,
        next A
        [,
        [~],
        With RPT,
        Word,
        ]Clock,
        , mod
        [
        [label] name src, src1
        }Table 446 Table 446 1b
        ] 2 2 N/R 2b CMP
        ]
        ]1 1 nR+3 3 CMPR
        2 2 N/R 4c CMPR
        , R5 1 1 nR+3 4d
        specified] STAT flags set by
        operation PC = PC +
        : RCF, RZF are set accordingly
        : TAG bit is set accordingly
      - 1844.14.11 CMPB Compare Two Bytes
      - 1854.14.12 CMPS Compare Two Strings
      - 1864.14.13 COR Correlation Filter Function
        With RPT
        1k
        y
        mask interrupts
      - 1874.14.14 CORK Correlation Filter Function
      - 1884.14.15 ENDLOOP End Loop
      - 1894.14.16 EXTSGN Sign Extend Word
      - 1904.14.17 EXTSGNS Sign Extend String
      - 1924.14.18 FIR FIR Filter Function (Coefficients in RAM)
      - 1944.14.19 FIRK FIR Filter Function (Coefficients in ROM)
      - 1954.14.20 IDLE Halt Processor
        Reduced Power Modes
      - 1964.14.21 IN Input From Port Into Word
        adrs}
        dest
      - 1974.14.22 INS Input From Port Into String
        n:
      - 1984.14.23 INTD Interrupt Disable
      - 1994.14.24 INTE Interrupt Enable
      - 2004.14.25 IRET Return From Interrupt
      - 2014.14.26 J
      - Conditional Jumps
        .
        = R
        Execution IF (condition = true OR unconditional) PC
        pma16
        ELSE NOP PC PC + 2 [if post modification specified] IF (
        ++)
        + 2 ELSE IF (
        )
        2 ELSE IF (
        ++R5)
        +R5 Flags Affected RCF and RZF affected by postmodification of R
        2024-110
        ,
        204See Also JMP, CALL, C
      - 2054.14.27 JMP Unconditional Jump
        Execution PC
        , CALL, C
        See Also J
        [Postmodify R
        if specified] Flags Affected RCF and RZF affected by postmodification of R
        Description
      - 2064.14.28 MOV Move Data Word From Source to Destination
        207[label]
        ]
        imm5
        ,
        imm4
        [, R
        
        }
        cc
        MOV TF
        [,
        clkdest, src,
        Clock,
        Word,
        ClassWith RPT,
        4-115
        name
        ] 1 1 N/R 8b MOV STR,
        1 1 N/R 9b MOV SV,
        1 1 N/R 9b MOV AP
        1 1 N/R 9c
        2084-116
        209Description Copy value of
        to
        . Premodification of accumulator pointers is allowed with some operand types.
      - 2124.14.29 MOVAPH Move With Adding PH
      - 2134.14.30 MOVAPHS Move With Adding PH
      - 2144.14.31 MOVB Move Byte From Source to Destination
        
        byte to
        Description Copy value of unsigned
        is {
        is R
        is A
        PC PC +
        byte.
      - 2164.14.32 MOVBS Move Byte String from Source to Destination
        4-125
      - 2174.14.33 MOVS Move String from Source to Destination
        [~], *A
        [~],
        }, *A
        pma16
        }, A
        [~], {
        With RPT,
        Word,
        Clock,
        }Table 446 Table 446 1a MOVS {
        [~]Table 446 Table 446 1a MOVS {
        Table 446 Table 446 1b
        nS+4 2 N/R 2b MOVSA
        [~], PH 1 1 1 3
        ~nS+2 1 nR+2 3
        [~] nS+4 1 nR+4 3
      - 2194.14.34 MOVSPH Move With Subtract from PH
        n
        n,
      - 2204.14.35 MOVSPHS Move String With Subtract From PH
        
        n
        adrs}
      - 2214.14.36 MOVT Move Tag From Source to Destination
      - 2224.14.37 MOVU Move Data Unsigned
    - 223Figure 48. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set
      - 2244.14.38 MUL Multiply (Rounded)
      - 2254.14.39 MULS Multiply String With No Data Transfer
      - 2264.14.40 MULAPL Multiply and Accumulate Result
      - 2274.14.41 MULAPLS Multiply String and Accumulate Result
      - 2284.14.42 MULSPL Multiply and Subtract PL From Accumulator
      - 2294.14.43 MULSPLS Multiply String and Subtract PL From Accumulator
      - 2304.14.44 MULTPL Multiply and Transfer PL to Accumulator
      - 2314.14.45 MULTPLS Multiply String and Transfer PL to Acumulator
      - 2324.14.46 NEGAC Twos Complement Negation of Accumulator
      - 2334.14.47 NEGACS Twos Complement Negation of Accumulator String
      - 2344.14.48 NOP No Operation
      - 2354.14.49 NOTAC Ones Complement Negation of Accumulator
      - 2364.14.50 NOTACS Ones Complement Negation of Accumulator String
      - 2374.14.51 OR Bitwise Logical OR
        Execution [premodify AP if
        , store result in
        and
        . Result is stored in
        and
        Description Bitwise OR of
        is {
        is TF
        is A
        PC PC +
        OR
        
        OR
        
        specified]
        bits in STAT register are set accordingly
        . If three operands are specified then logical OR
        . Premodification of accumulator pointers are allowed with some operand types.
      - 2394.14.52 ORB Bitwise OR Byte
      - 2404.14.53 ORS Bitwise OR String
      - 2414.14.54 OUT Output to Port
      - 2424.14.55 OUTS Output String to Port
      - 2434.14.56 RET Return From Subroutine (CALL, C
      - )
      - 2444.14.57 RFLAG Reset Memory Flag
      - 2454.14.58 RFM Reset Fractional Mode
      - 2464.14.59 ROVM Reset Overflow Mode
      - 2474.14.60 RPT Repeat Next Instruction
        mask interrupt
      - 2484.14.61 RTAG Reset Tag
      - 2494.14.62 RXM Reset Extended Sign Mode
      - 2504.14.63 SFLAG Set Memory Flag
      - 2514.14.64 SFM Set Fractional Mode
      - 2524.14.65 SHL Shift Left
      - 2534.14.66 SHLAC Shift Left Accumulator
      - 2544.14.67 SHLACS Shift Left Accumulator String Individually
      - 2554.14.68 SHLAPL Shift Left with Accumulate
      - 2564.14.69 SHLAPLS Shift Left String With Accumulate
      - 2574.14.70 SHLS Shift Left Accumulator String to Product
      - 2584.14.71 SHLSPL Shift Left With Subtract PL
      - 2594.14.72 SHLSPLS Shift Left String With Subtract PL
      - 2604.14.73 SHLTPL Shift Left and Transfer PL to Accumulator
      - 2614.14.74 SHLTPLS Shift Left String and Transfer PL to Accumulator
      - 2624.14.75 SHRAC Shift Accumulator Right
      - 2634.14.76 SHRACS Shift Accumulator String Right
      - 2644.14.77 SOVM Set Overflow Mode
      - 2654.14.78 STAG Set Tag
        
        4-174
      - 2664.14.79 SUB Subtract
        ,
        ) and store result in
        -
        from value of
        and store result in
        from value of
        Description Subtract value of
        is {
        is R
        is A
        PC PC +
        
        Execution [premodify AP if
        SUB R
        next A
        [,
        next A
        ~ [,
        next A
        [~], PH [,
        next A
        [,
        [~],
        } [,
        With RPT,
        Word,
        ]] Clock,
        , [
        src1
        ,
        ]Table 446 Table 446 1a
        ] 2 2 N/R 2b
        2 2 N/R 4c SUB R
        , R5 1 1 N/R 4d
        specified]
        . If three operands are specified, then subtract value of
        (i.e.,
      - 2684.14.80 SUBB Subtract Byte
        4-177
      - 2694.14.81 SUBS Subtract Accumulataor String
        pma16
        ) and store result in
        string (i.e.,
        string from value of
        string from value of the
        Description Subtract the value of the
        [~],
        is {
        is A
        PC PC +
        
        Execution [premodify AP if
        With RPT,
        pma16
        Word,
        Clock,
        [label] name dest, src, src1
        }Table 446 Table 446 1a
        ns+4 2 N/R 32b
        ~ns+2 1 nR+2 3
        ns+2 1 nR+2 3 SUBSA
        [~], PH 1 1 1 3
        specified]
        string and store the result in the
        string. If three operands are specified, then subtract value of
      - 2714.14.82 SXM Set Extended Sign Mode
      - 2724.14.83 VCALL Vectored Call
        vector8
      - 2734.14.84 XOR Logical XOR
        Execution [premodify AP if
        , store the result in
        and
        . Result is stored in
        and
        Description Bitwise logical XOR of
        is {flag
        is {
        is TF
        is A
        PC PC +
        XOR
        
        XOR
        
        specified]
        bits in STAT register are set accordingly
        . If three operands are specified, then logical XOR
        . Pre- modification of accumulator pointers is allowed with some operand types.
      - 2754.14.85 XORB Logical XOR Byte
      - 2764.14.86 XORS Logical XOR String
      - 2774.14.87 ZAC Zero Accumulator
      - 2784.14.88 ZACS Zero Accumulator String
        4-187
  - 2794.15 Instruction Set Encoding
  - 2884.16 Instruction Set Summary
301Code Development Tools
- Chapter 5
  - 3025.1 Introduction
    - Figure 51. Level Translator Circuit
  - 3035.2 MSP50C6xx Software Development Tool
  - 3045.3 Requirements
  - 3055.4 Hardware Installation
    - Figure 52. Hardware Installation
      - Software Installation
      - 5-6
    - Figure 53. 10-Pin IDC Connector (top view looking at the board)
  - 3065.5 Software Installation
    - Figure 54. InstallShield Window
    - 307Figure 55. Setup Window
    - 309Figure 58. Choose Destination Location Dialog
    - 310Figure 59. Select Program Folder Dialog
    - 312Figure 511.Setup Complete Dialog
  - 3135.6 Software Emulator
    - 5.6.1 The Open Screen
    - Figure 512. Open Screen
      - Project
    - 315Figure 515. File Menu Options
      - 5.6.2 Projects
        make
        build
        activated
        simulator
    - 317Figure 517. RAM Window
      - tag bit
    - 318Figure 518. CPU Window
      - time
    - 319Figure 519. Program Window
      - gray area
    - 320Figure 520. Hardware Breakpoint Dialog
    - 322Figure 523. I/O Ports Window
      - inclusion
      - gray area
      - 5.6.4 Debugging a Program
    - 323Figure 524. Debug Menu
      - 324at a time
      - animation
      - Error: No more software breakpoint
      - animated
      - fast
      - trace mode
    - 326Figure 526. Trace Mode
      - 5.6.5 Initializing Chip
    - 327Figure 527. Init Menu Option
      - 3285.6.6 Emulator Options
        Verbose C
        Chip Select...
        Misc...
        Debugging
    - 329Figure 528. Options Menu
    - Figure 529. Miscellaneous Dialog
    - 330Figure 530. Windows Menu Options
      - 5.6.7 Emulator Online Help System
        Help
      - 3325.6.8 Known Differences, Incompatibilities, Restrictions
        char
        extern
        int
  - 3335.7 Assembler
    - 5.7.1 Assembler DLL
    - 3345.7.2 Assembler Directives
      - 335function table
      - Users should NEVER use this directive in an assembly language program.
      - 336function table
      - Users should NEVER use this directive in an assembly language program.
      - 337expression
      - label
      - filename
      - text_string
  - 3385.8 Linker
  - 3395.9 C Compiler
    - imperative
    - 3405.9.1 Foreword
      - high level
        C Compiler
        5-41
    - 3415.9.2 Variable Types
      - string of integer
      - dummy
      - const
      - constant
      - single
      - n 16 bit integers
      - long
    - 5.9.3 External References
    - 3425.9.4 C Directives
      - 5.9.4.1 #define
      - #undefine
      - undefine
      - defined
      - 5.9.4.2 #undefine
    - 3445.9.5 Include Files
      - cmm_func
      - regular
    - 3455.9.6 Function Prototypes and Declarations
      - cmm_func.
    - 5.9.7 Initializations
    - 5.9.8 RAM Usage
    - 5.9.9 Variable Types
    - 5.9.10 String Functions
      - C Compiler
    - 346Table 51. String Functions
      - 3475.9.11 Constant Functions
        constant
  - 3485.10 Implementation Details
    - 5.10.1 Comparisons
      - 349absolute
    - 3505.10.2 Division
    - 5.10.3 Function Calls
    - 3515.10.4 Programming Example
    - 3535.10.5 Programming Example, C With Assembly Routines
  - 3675.11 Beware of Stack Corruption
  - 5.12 Reported Bugs With Code Development Tool
369Applications
- Chapter 6
  - Application Circuits
  - 3706.1 Application Circuits
    - 371Application Circuits
    - Important Note regarding Scan Port Bond Out
    - strongly
    - footprint
  - 3726.2 MSP50C614/MSP50P614 Initialization Codes
    - jump
    - must not
    - 3736.2.1 File init.asm
  - 3766.3 Texas Instruments C614 Synthesis Code
    - Project New Project
    - Init Init All
    - Debug Eprom Programming
    - Project Build
    - Blank Check + Program
    - 377Extra, extra, read all about it
    - Extra, extra etc
    - character voice
    - character
    - rolling one
    - 380File Insert
    - bytes
    - words
    - 3816.3.1 Memory Overlay
  - 3826.4 ROM Usage With Respect to Various Synthesis Algorithms
383Customer Information
- Chapter 7
  - 3847.1 Mechanical Information
    - 7.1.1 Die Bond-Out Coordinates
    - 7.1.2 Package Information
    - 385Table 71. MSP50C614 100-Pin PJM Plastic Package Pinout Description
      - 7-4
    - 386Figure 71. 100-Pin PJM Mechanical Information
    - 387Figure 72. 120-Pin Grid Array Package for the Development Device, P614
      - M
      - Note: The PGA package is only available in limited quantities for development purposes.
    - 388Figure 73. 120 Pin Grid Array (PGA) Package Leads, P614
  - 3897.2 Customer Information Fields in the ROM
  - 3907.3 Speech Development Cycle
    - Figure 74. Speech Development Cycle
  - 7.4 Device Production Sequence
  - 3927.5 Ordering Information
  - 7.6 New Product Release Forms
    - 393New Product Release Forms
395MSP50C605 Preliminary Data
- 396A.1 Introduction
- A.2 Features
- A.3 Architecture
  - 397A.3.1 RAM
  - A.3.2 ROM
  - A.3.3 I/O Pins
    - A-4
  - 398Figure A1. MSP50C605 Architecture
    - A-5
    - MSP50C605 Preliminary Data
  - 399Figure A2. MSP50C605 Memory Organization
    - User ROM 30704 x 17 bit (C605 : readonly) (P614 : EPROM)
    - 229,376 x 8 bit
      - RESET vector
      - (reserved)
      - Internal Test Code 2048 x 17 bit (reserved )
    - Data ROM
    - Program Memory Peripheral Ports
    - Data Memory
      - RAM 640 x 17 bit
      - Usable Interrupt Vectors 8 x 17 bit
      - DATA ROM (slow)
        MSP50C605 Preliminary Data
  - 401Table A1. MSP50C605 100-Pin PJM Plastic Package Pinout Description
403MSP50C604 Preliminary Data
- 404B.1 Introduction
- B.2 Features
- B.3 Architecture
  - 405B.3.1 RAM
  - B.3.2 ROM
    - slave
    - host
  - B.3.3 I/O Pins
    - B-4
  - 406Figure B1. MSP50C604 Block Diagram
    - 407B.3.4 Slave Mode Operation
    - B.3.5 Host Write Sequence
    - B.3.6 Host Read Sequence
  - 408Figure B2. MSP50C604 Memory Organization and I/O ports
    - RESET vector
    - 409B.3.7 Interrupts
      - Packaging
- 410B.4 Packaging
  - The MSP50C604 is sold in die form. A 64 pin plastic package is also available.
  - Table B1. MSP50C604 64-Pin PJM Plastic Package Pinout Description
    - Packaging
    - MSP50C604 Preliminary Data
  - Figure B3. MSP50C604 Slave Mode Signals
  - Figure B4. MSP50C604 64-Pin PJM Package
- 411MSP50C604 64 PIN PJM PLASTIC PACKAGE

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