Texas Instruments MSP50C614 manual ±6. Data Memory Address Unit, RAM Configuration

Data Memory Address Unit

Figure 2±6. Data Memory Address Unit

	Arithmetic Block
R0
R1
R2
R3
R4	LOOP
R5	INDEX
R6	PAGE
R7	STACK
	Register	Addressing Mode

Internal

Databus

Internal Program Bus

RAM Address

2.3.1RAM Configuration

The data memory block (RAM) is physically organized into 17-bit parallel words. Within each word, the extra bit (bit 16) is used as a flag bit or tag for op-codes in the instruction set. Specifically, the flag bit directs complex branch conditions associated with certain instructions. The flag bit is also used by the computational unit for signed or unsigned arithmetic operations (see Section 2.2.1, Multiplier).

The size of the C614 RAM block is 640 17-bit locations. Each address provided by the DMAU causes 17 bits of data to be addressed. These 17 bits are operated on in different ways, depending on the instructions being executed. For most instructions, the data is interpreted as 16-bit word format. This means that bits 0 through 15 are used, and bit 16 is either ignored or designated as a flag or status bit.

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