Texas Instruments MSP50C614 manual Interrupt/General Control Register

Interrupt/General Control Register

The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the enable bit for the pull-up resistors on input port F. Setting this bit engages all 8 F-port pins with at least 100-kΩpull-ups (see Section 3.1.2, Dedicated Input Port F)

Bit 13 is the PDMCD bit for the pulse-density modulation clock. Clearing this bit yields a PDM clock rate equal to one-half the frequency of the master clock (i.e., the CPU clock rate). Setting bit 13 yields a PDM rate equal to the rate of the master clock (see Section 3.2.3, PDM Clock Divider)

Bit 14 is the ARM bit. The set ARM bit causes an asynchronous response to the internal and external interrupts during the sleep state. If the master clock has been suspended during sleep, then the ARM bit must be set (before the IDLE instruction), in order to allow a programmable interrupt to wake the C614. Refer to Section 2.11, Reduced Power Modes, for more information.

Finally, the top-most bit in the IntGenCtrl is the comparator enable bit. Setting bit 15 enables the comparator and all of its associated functions. Some of the C614's conditions, interrupts, and timers behave differently, depending on whether the comparator is enabled or disabled by this bit. Refer to Section 3.3, Comparator, for a full description.

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