Interrupt/General Control Register

3.4 Interrupt/General Control Register

The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The service branch enable status for each of the eight interrupts is registered in the IMR. A SET bit in the IMR enables that interrupt to assume the service branch (at the time that the associated trigger event occurs). A CLEAR bit disables the service branch for that interrupt. The IMR is located at bits 0 through 7 in the IntGenCtrl. Bit 0 is associated with INT0, which is the highest priority interrupt. Bit 7 is associated with INT7. Refer to Section 2.7, Interrupt Logic, for more information regarding the interrupt-system logic and initialization sequence.

IntGenCtrl register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address 0x38

(16-bit wide location)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

 

 

 

CE

AR

PD

EP

E2

E1

S2

S1

 

D5

D4

PF

D3

D2

T2

T1

DA

 

 

 

 

 

 

 

 

 

 

 

low

 

 

 

 

 

 

high

 

 

 

 

 

 

 

 

 

 

priority

 

 

 

 

priority

0x0000 : State after RESET low

 

 

 

 

 

Interrupt mask register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE : Comparator enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D5

: port D5 falling-edge

 

 

 

 

 

AR : ARM bit

 

 

 

 

 

 

 

D4

: port D4 rising-edge

 

 

 

 

 

PD : Pulse-density clock: PDMCD

 

 

 

 

D3

: port D3 falling-edge

 

 

 

 

 

EP : Enable pullup resistors on port F

 

 

 

 

D2

: port D2 rising-edge

 

 

 

 

 

E2

: Enable TIMER2 (1 value starts timer)

 

 

 

PF

: any port F falling-edge

 

 

 

 

E1

: Enable TIMER 1 (1 value starts timer)

 

 

 

T2 : TIMER2 underflow

 

 

 

 

 

S2

: Clock source for TIMER2 (0 chooses 1/2 MC)

 

 

T1 : TIMER1 underflow

 

 

 

 

 

S1

: Clock source for TIMER1 (0 chooses 1/2 MC)

 

 

DA : DAC timer underflow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1 value enables interrupt service)

The remaining bits in the IntGenCtrl have various control functions which are not directly related to the interrupt system. Four of these are related to the timer functions. Bits 8 and 9 are used to select the clock sources which govern the rates of TIMER1 and TIMER2. Clearing bit 8 chooses 1/2 MC as the source for TIMER1 (i.e., the TIMER runs at one-half the frequency of the Master Clock). Setting bit 8 chooses the oscillator reference (RTO or CRO) as the source for TIMER1. (The same applies for bit 9 and TIMER2.) Bits 10 and 11 in the IntGenCtrl are used to enable TIMER1 and TIMER2, respectively. Setting bit 10 starts TIMER1, and clearing bit 10 stops TIMER1. (The same applies for bit 11 and TIMER2).

Peripheral Functions

3-17

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Image 87
Texas Instruments MSP50C614 manual Interrupt/General Control Register, IntGenCtrl register

MSP50C614 specifications

The Texas Instruments MSP50C614 is a microcontroller that belongs to the MSP430 family, renowned for its low power consumption and versatile functionality. Primarily designed for embedded applications, this microcontroller is favored in various industries, including consumer electronics, industrial automation, and healthcare devices.

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The MSP50C614 is equipped with a 16-bit RISC CPU that delivers high performance while maintaining low power usage. With a maximum clock frequency of 16 MHz, it can execute most instructions in a single cycle, resulting in swift operation and responsive performance. This microcontroller also comes with a generous flash memory capacity, allowing developers to store large amounts of code and data conveniently.

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