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Texas Instruments MSP50C614 manual Rflag Reset Memory Flag, Sflag , Stag , Rtag

Models: MSP50C614

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Individual Instruction Descriptions

4.14.57 RFLAG					Reset Memory Flag
Syntax

	[label]		name		src									Clock, clk			Word, w					With RPT, clk							Class

			RFLAG		{flagadrs}										1			1						N/R					8a
Execution			memory flag bit at {flagadrs} data memory location ⇐																		0
			PC ⇐ PC + 1
Flags Affected			None
Opcode

Instructions				16			15	14	13		12	11		10	9	8	7	6		5		4		3	2		1			0

RFLAG {flagadrs}				1			0	0	1		0	0		0	0	1	1						flagadrs
Description			Reset flag at addressed memory location to 0.{flagadrs} includes two groups
			of memory flag addresses: global flags, which are the first 64 word locations
			in RAM; and relative flags, which are 64 locations relative to the page register
			(R6). Flag address {flagadrs} only addresses the 17th bit. (See section 4.3.7
			for more information)
See Also			SFLAG, STAG, RTAG
Example 4.14.57.1			RFLAG *0x21

Resets the flag bit at RAM byte location 0x0042 to zero.

Example 4.14.57.2 RFLAG *R6 + 0x0002

Resets the flag bit at RAM byte location 0x0084 to zero. Assume R6 = 0x0080. The R6 register is represented in bytes, but the 0x0002 is represented in words. Thus, 0x0080 bytes plus 0x0002 words (or 0x0004 bytes) equals 0x0084 (bytes).

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Image 244

Texas Instruments MSP50C614 manual Rflag Reset Memory Flag, Sflag , Stag , Rtag, Example 4.14.57.2 Rflag *R6 +

Contents

MSP50C614 Mixed-Signal Processor Users Guide Important Notice How to Use This Manual About This ManualNotational Conventions This document uses the following conventionsThis provides three choices *, *+, or *± Csr ±a /user/ti/simuboard/utilitiesNotational Conventions Information About Cautions and Warnings TrademarksThis book may contain cautions and warnings Information About Cautions and WarningsPage Contents Assembly Language Instructions ContentsContentsix Code Development ToolsApplications ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Contentsxi Figures ±10 ±11±12 ±13Tables ±32 ±33±34 ±35Page Introduction to the MSP50C614 Features of the C614 Features of the C614Applications ApplicationsIntroduction to the MSP50C614 Development Device MSP50P614 Development Device MSP50P614Functional Description Functional DescriptionC605 and C604 Preliminary Information C605 and C604 Preliminary Information±1. Functional Block Diagram for the C614 Crystal Oscillator Operation Connections Resistor Trim Operation Connections±3. Reset Circuit ±1. Signal and Pad Descriptions for the C614 Terminal Assignments and Signal DescriptionsTerminal Assignments and Signal Descriptions ±2. MSP50C614 100-Pin PJM Plastic Package Pinout Description Description Pin #PD0 PD1 PD2 PD3 PD4 PD5 PD6 ±5 Pin Grid Array Package for the Development Device, P614 VPP VSS VDD DAC M DAC P MSP50C614 Architecture Architecture Overview ±1. MSP50C614 Core Processor Block Diagram MSP50C614 ArchitectureALU Computation Unit Multiplier±1. Signed and Unsigned Integer Representation Computation UnitComputation Unit ±3. Overview of the Multiplier Unit Operation Arithmetic Logic UnitAccumulator Block ±4. Overview of the Arithmetic Logic Unit Accumulator Block AC0 . . . AC31Accumulator Block Pointers AP0 . . . AP3Data Memory Address Unit Data Memory Address UnitRAM Configuration ±6. Data Memory Address UnitData Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM ±7. C614 Memory Map not drawn to scale Peripheral Communications PortsReset LOW ±2. Summary of C614s Peripheral Communications PortsInterrupt Vectors Interrupt Name ROM address Event Source Interrupt PriorityROM Code Security Block Protection Word Write only= the value programmed at TM5… TM0 true Protection marker≡ the binary complement of NTM = the value programmed at FM5… FM0 falseMacro Call Vectors Interrupt LogicInterrupt Logic IFR Interrupt Logic ±8. Interrupt Initialization Sequence Timer Registers Timer RegistersTriggers INT1 on underflow Timer Registers Clock Control Oscillator OptionsPLL Performance Clock Control±9. PLL Performance Clock Speed Control RegisterCPU ClkSpdCtrl registerRtrim Register Read Only Applies to MSP50C614 Device Only RTO Oscillator Trim AdjustmentClkSpdCtrl Value Copied Shaded Execution Timing Execution TimingReduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes ±3. Programmable Bits Needed to Control Reduced Power Modes Light MID DeepComponent Determined → deeper sleep … relatively less power →By Controls Deeper sleep … Relatively less power → Event Determined Global interrupt enable is SET Peripheral Functions General-Purpose I/O Ports I/OPort a Port B Port C Port D Port E Peripheral Functions Dedicated Input Port F Input Port FDedicated Output Port G Totem-Pole Output Port GBranch on D Port Internal and External Interrupts±1. Interrupts Interrupt Vector Source Trigger Event Priority CommentDigital-to-Analog Converter DAC Pulse-Density Modulation RateDAC Control and Data Registers Digital-to-Analog Converter DACOverflow bits Least-significant data value Ignored bits PDM Clock Divider ±1. PDM Clock DividerDigital-to-Analog Converter DAC CPU Pllm Comparator For INT7 is enabled TIMER1 starts countingCleared. Refer to .7, Interrupt Logic, for more details AddressComparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Interrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States Bit Bit Name Initialized Value Description RZFPage Assembly Language Instructions Introduction System RegistersTop of Stack, TOS Assembly Language InstructionsSystem Registers Product Low Register PL Product High Register PHAccumulators AC0±AC31 Indirect Register R0±R7 Accumulator Pointers AP0±AP3Bit String Register STR Status Register Stat±1. Status Register Stat FunctionInstruction Syntax and Addressing Modes 1 MSP50P614/MSP50C614 Instruction Syntax±2. Addressing Mode Encoding Addressing ModesOpcode Next a±4. Addressing Mode Bits and adrs Field Description ±3. Rx Bit Description±5. MSP50P614/MSP50C614 Addressing Modes Summary ±6. Auto Increment and Auto Decrement ModesFlag addressing mode encoding, flagadrs Flag RepeatFlagadrs Clocks Words Addressing Operation, ² SyntaxSyntax Immediate AddressingExample MOV *0x012F * 2, *A0 Direct AddressingMulr *0x02A1 ±9. Indirect Addressing Syntax Indirect AddressingSyntaxOperation Relative Addressing MOV A2, *R0*R4++ Movb *R7++, A3A0, *R3+R5 Short RelativeMOV A3, *R6+0x10 Long RelativeFlag Addressing TF1, *0x20Or TF2, *R6+0x02 XOR TF1, *R6+0x208 Tag/Flag Bits Possible sources of confusion Consider the following code TF1,*ram1 TF1 bit in Stat is set!?±10. Symbols and Explanation Symbol ExplanationInstruction Classification Instruction Classification±11. Instruction Classification ±11. Symbols and ExplanationClass Sub- Description Class Sub Description ±12. Classes and Opcode Definition Class 1 Instructions Memory and Accumulator Reference±13. Class 1 Instruction Encoding ±14. Class 1a Instruction DescriptionC1a ~A~ C1b±15. Class 1b Instruction Description C1b Mnemonic DescriptionClass 2 Instructions Accumulator and Constant Reference Shltpls a n, adrs±17. Class 2a Instruction Description ±16. Class 2 Instruction EncodingC2a Mnemonic Description ±18. Class 2b Instruction Description Class 3 Instruction Accumulator ReferenceC2b Mnemonic Description ADD An ~, An ~, imm16 , next a±20. Class 3 Instruction Description ±19. Class 3 Instruction EncodingMnemonic Description Zero or be set equal to the sign bit Xsgm dependent MOV SV, An~ , next a Class 4 Instructions Address Register and Memory Reference ±21. Class 4a Instruction Encoding±22. Class 4a Instruction Description ±23. Class 4b Instruction Description±24. Class 4c Instruction Description ±25. Class 4d Instruction Description±26. Class 5 Instruction Encoding Class 5 Instructions Memory Reference±27. Class 5 Instruction Description RET² Class 6 Instructions Port and Memory Reference ±28. Class 6a Instruction Encoding±29. Class 6a Instruction Description C6a Mnemonic DescriptionClass 7 Instructions Program Control ±30. Class 6b Instruction DescriptionC6b Mnemonic Description ±31. Class 7 Instruction Encoding and Description Vector8Jcc CccClass 8 Instructions Logic and Bit ±32. Class 8a Instruction Encoding±33. Class 8a Instruction Description ±34. Class 8b Instruction DescriptionClass 9 Instructions Miscellaneous C8a Mnemonic Description±35. Class 9a Instruction Encoding ±36. Class 9a Instruction Description±37. Class 9b Instruction Description C9a Mnemonic DescriptionBit, Byte, Word and String Addressing ±38. Class 9c Instruction Description±39. Class 9d Instruction Description C9c Mnemonic Description±3. Data Memory Organization and Addressing Mode Address Used Data Order Rx Post modify ² ±40. Data Memory Address and Data RelationshipMovb A0, *0x0003 MOV A0, *0x0004±4. Data Memory Example Which uses the absolute word memory addressRflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational ModesComputational Setting Resetting Function Mode Instruction ±41. MSP50P614/MSP50C614 Computational ModesSXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop Instructions±42. Hardware Loops in MSP50P614/MSP50C614 Syntax Operation LimitationsString Instructions ±43. Initial Processor State for String InstructionsString Instructions Registers register# = valueMulapl A0, A0~ Lookup Instructions ±44. Lookup InstructionsLookup Instructions Instructions Description Data TransferMOV An, adrs SUB An MOV An, *An Input/Output Instructions Special Filter InstructionsInput/Output Instructions Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-mSpecial Filter Instructions STR,N±2 STR,0 0x0104 After FIR/COR execution Important note about setting the Stat register Firkcoeffs Coeffarray address FIRK/CORK only Program memory FIRK/CORK Coeffarray Samplebuf addressFIR/COR only = 0..N CoeffarraySamplebuf Coeffarray is stored Conditionals ConditionalsSymbol Meaning Operands≤ dma6 ≤ ≤ dma16 ≤ ≤ port4 ≤ ≤ port6 ≤Adrsn ClkDma n FlgPma n Offset nPort n ±45. Auto Increment and Decrement ±46. Addressing Mode Bits and adrs Field Description±47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions14.1 ADD Add word ExecutionDescription See AlsoPC PC + Flags Affected AddbOpcode Adds Add String Clock , clk Words , wAdds A1, A1~, A1 14.4 Bitwise A3, *R4Ð± ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 Andb Bitwise and Byte Src byte PC PC +OF, SF, ZF, CF are set accordingly Clock , clk Word , wAnds Bitwise and String Ands A0, A0~, A0Ands A0, A0~, *R2 Clock, clk Word, wBegloop Begin Loop Save next instruction address PC +Flags Affected None Opcode Order to loop N timesCall Unconditional Subroutine Call TOS TOS PC +R7 + NOP±48. Names for cc True condition Not true conditionSyntax Alternate Syntax Description CALL, VCALL, RET, Iret 0x2010CTF1 Crnbe14.10 CMP Compare Two Words Stat flags set by src ± src1 operationPC = PC + w CMPB, CMPS, Jcc, CccCMP R2, 0xfe20 CMP R0, R5Cmpb Compare Two Bytes Cmpb R3Cmps Compare Two Strings PC PC + w Flags AffectedCmps A1~ Cmps A2, A2~14.13 COR Correlation Filter Function 3n R+2Xeven = R xeven + R5 Xeven ++Cork Correlation Filter Function Sample data. During Cork execution, interrupt is queuedAn, *Rx 3nR+2 Rxeven = Rxeven + R5Endloop End Loop Decrement R4 by n 1 or First address after Begloop ElseArgument, it assumes n =1 BEGLOOP, InteExtsgn Sign Extend Word An~ , next aCopy accumulator sign flag SF to all 16 bits of An~ Dest , modExtsgns Sign Extend String DestExtsgn 14.18 FIR FIR Filter Function Coefficients in RAM 2n R+2Assembly Language Instructions 101 Be even. During Firk execution, interrupts are queued FirkRPT, FIR, COR, Cork Idle Halt Processor Assembly Language Instructions 103Stop processor clocks INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d 14.22 INS Input From Port Into String IN, OUT, OutsIntd Interrupt Disable IM is Stat bitStat to INTE, IretAssembly Language Instructions 107 Inte Interrupt EnableINTD, Iret Iret Return From Interrupt R7 R7 ±See Also RET, CALL, C cc, INTE, Intd Description Return from interrupt. Pop top of stack to program counter14.26 Jcc Conditional Jumps PC PC +110 If test condition is false, a NOP is executed See Also JMP, CALL, C cc Example JNZJE 0x2010, R3++R5 JIN1 0x2010, R1±±14.27 JMP Unconditional Jump Post±modify Rx if specifiedRCF and RZF affected by post±modification of Rx See Also Jcc, CALL, Ccc Example14.28 MOV Move Data Word From Source to Destination XSF, XZF are set accordingly Clock, clk Word, w With RPT, clk ClassTFn, cc , Rx STR, imm8116 With some operand types MOVU, MOVT, MOVB, MOVBS, Movs Example 4.14.28.10 MOV MR, A3, ±±AExample 4.14.28.11 MOV A1~, *A1 Example 4.14.28.12 MOV *0x0200 * 2, R0Example 4.14.28.13 MOV R1, 0x0200 Example 4.14.28.15 MOV *0x0200 * 2, R0Transfer R5 to R0 Example Example 4.14.28.18 MOV *R6 + 8 * 2, DPExecution + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaphs Move With Adding PH Execution An + PHBackground. See .8 for more details MOVAPH, MOVTPH, MOVTPHS, MOVSPH, MovsphsMovb Move Byte From Source to Destination Copy value of unsigned src byte to dest byteMovb A0, *R2 Copy data memory byte pointed by R2 to accumulator A0Movb A0, 0xf2 Movb *R2, A0Movb R2 Movbs Move Byte String from Source to Destination TAG bit is set to bit 17 th valueMovbs A2, *0x0200 Movbs *0x0200, A2Movs Move String from Source to Destination Movs A1, A1~ Movs A2~Movs A1~, A1 Movsph Assembly Language Instructions 127MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Second word ± PH MR contents of adrs Movsphs Move String With Subtract From PHDetails MOVSPH, MOVAPH, MOVAPHS, MOVTPH, MovtphsMovt PC PC + w Flags Affected None OpcodeAvailable MOVU, MOV, MOVT, MOVB, MOVBS, MovsMovu Move Data Unsigned TAG bit is set accordingly UM is set toMOV, MOVB, MOVT, MOVBS, Movs Copy the value pointed by R3 to MRAssembly Language Instructions 131 14.38 MUL Multiply Rounded MR * src PC PC + w Flags AffectedAccumulator pointer if specified MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MulaplLength nS+2, where nS is the value in STR register Muls Multiply String With No Data TransferPH,PL MR * src string MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MultplsMulapl Multiply and Accumulate Result PH ,PL MR * srcBackground. See .8 for more detail MULAPLS, MULSPL, MULSPLS, MULTPL, MultplsMR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulspl Multiply and Subtract PL From Accumulator Occuring in the background. See .8 for more detailsMULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspl adrsMulspls Multiply String and Subtract PL From Accumulator From dest stringMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspls adrsMultpl Multiply and Transfer PL to Accumulator Multpls Execution PH, PL MR * src PC PC + Flags AffectedStored in An string MULTPL, MULAPL, MULAPLS, MULSPL, MulsplsNegac Twos Complement Negation of Accumulator AccumulatorNEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Example 4.14.46.1 Negac A3~, A3, ±±AAssembly Language Instructions 141 Negacs Twos Complement Negation of Accumulator StringDest accumulator string NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NotacsExecution PC PC + 14.48 NOP No OperationRPT Notac Ones Complement Negation of Accumulator NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, XorsNEGAC, Negacs Example 4.14.49.1 Notac A3~, A3, ±±ANotacs Ones Complement Negation of Accumulator String Accumulator stringNegacs A3~TFn bits in Stat register are set accordingly 14.51 or Bitwise Logical orAccumulator pointers are allowed with some operand types Or A0, *R0++R5 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr TF1, *R6+0x22 14.52 ORB Bitwise or Byte Or srcAccumulator is affected OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs14.53 ORS Bitwise or String PC + w Flags AffectedOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs ORS A0, A0~, A0Address is multipled by 4 to get the actual port address 14.54 OUTOUTS, IN, INS Outs Output String to Port Port6 specified in the instructionOUT, IN, INS Port6 , An ~Assembly Language Instructions 151 14.56 RET Return From Subroutine CALL, CccPC TOS CALL, i.e., RET followed by a RET should not be allowedSflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.57.2 Rflag *R6 + Reset Fractional Mode Syntax Resets the fractional mode. Clears FM bit of Stat14.58 RFM STAT.FMRovm Reset Overflow Mode Saturation output normal modeResets the overflow mode to zero Stat .OM14.60 RPT Repeat Next Instruction Load src to repeat counterLoad imm8 to repeat counter After execution completesRtag Reset Tag Stag , Rflag , SflagRtag *R6+0x0002 Rtag *R6+0x000314.62 RXM Reset Extended Sign Mode Assembly Language Instructions 157STAT.XM SXMSflag Set Memory Flag Address flagadrs only accesses the 17 th bitRflag , Stag , Rtag 14.64 SFM Set Fractional Mode Mode for signed fractional arithmeticAssembly Language Instructions 159 Set fractional mode. Set FM bit of Stat to14.65 SHL Shift Left PH , PLAccumulator. Use Shlac for this purpose ShlsShlac Shift Left Accumulator Its offset. LSB of result is set to zeroShift accumulator A1 by one bit to the left Example 4.14.66.2 Shlac A1~, A1, ±±AShlacs Shift Left Accumulator String Individually Accumulators in the stringShlapl Shift Left with Accumulate Example 4.14.68.1 Shlapl A0, *R4++R5Shlapl A2, *R1++ Example 4.14.68.3 Shlapl A1, A1, ++AShift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ Assembly Language Instructions 165 Shls Shift Left Accumulator String to ProductExecution PH, PL An~Shlspl Shift Left With Subtract PL Example 4.14.71.1 Shlspl A0, *R4++R5Shlspl A2, *R1++ Example 4.14.71.3 Shlspl A1, A1, ++AShlspls Shift Left String With Subtract PL Bit to the next accumulatorShlspl , Shltpl , SHLTPLS, SHLAPL, Shlapls Syntax Description Shlspls An, adrsShltpl Shift Left and Transfer PL to Accumulator Example 4.14.73.1 Shltpl A0, *R4++R5Shltpl A2, *R1++ Example 4.14.73.3 Shltpl A1, A1, ++AShltpls Shift Left String and Transfer PL to Accumulator Execution PH, PL src SVReceives the same data as PH SHLTPL, SHLAPL, SHLAPLS, SHLSPL, ShlsplsShrac Shift Accumulator Right RegisterShift right one bit the accumulator A1 Example 4.14.75.2 Shrac A1~, A1, ++AAssembly Language Instructions 171 Shracs Shift Accumulator String RightSHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl ShltplsSet Overflow Mode Syntax Output DSP modeSovm STAT.OMRTAG, RFLAG, Sflag StagStag *0x401 14.79 SUB Subtract Dest, src , src1 , next aAn ~ , An , adrs , next a An ~ , An ~ , imm16 , next aExample 4.14.79.2 SUB A0, A0, 2, ++A SUB A1, A1~, A1SUB A3~, A3, *R4Ð SUB R3, R5Subb Subtract Byte Subtract 0x45 from accumulator A2 byteSubtract 0xF2 from register R3 byte Syntax Description Subb a n, imm8Assembly Language Instructions 177 Subs Subtract Accumulataor StringSubs A2, A2~, A2 Subs A2, A2, A2~Subs A3~, A3~, PH 14.82 SXM Set Extended Sign Mode Sets extended sign mode status register Stat bit 0 toAssembly Language Instructions 179 RXMVcall Vectored Call Push PC + 0x7F00R7 R7 + Flags Affected See Also RET, IRET, CALL, C cc Example14.84 XOR Logical XOR XOR src For two operandsXOR src For three operands TAG bit is set accordingly Src is flagadrsExample 4.14.84.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.84.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 183XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors Logical XOR String Dest stringXOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A2Reset the content of accumulator A0 to zero Assembly Language Instructions 18514.87 ZAC Zero Accumulator ZacsReset the content of offset accumulator string A1~ to zero Zacs Zero Accumulator StringPC PC + Flags Affected ZF = Zero the specified accumulator stringInstruction Set Encoding Assembly Language Instructions 187Instruction Set Encoding 188 Assembly Language Instructions 189 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 True condition Not true conditionInstruction Set Summary Pma16 , Rmod Assembly Language Instructions 197 An~, An~ , next aAn~, imm16 , next a Rx, R5Adrs, a n~ , next a ±46 ~, adrs , next a ±46Adrs , *An ±46 An ~, imm16 , next aAssembly Language Instructions 199 Adrs, SVAdrs, APn Adrs, TOSMR, adrs ~ , next a~, a n~ , next a ~ , a n~An~, An~ , next a NR+3 Assembly Language Instructions 201 TFn, flagadrs NR+3 TFn, cc , RxAn~, An~, pma16 An~, An~, An~, a n~ ~, a n, a n~ , next a~, a n, a n~ ~, a n~, PHConditional on RCF=1 Not condition RCF=0 Conditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1Conditional on RZF=1 Not condition RZF=0 Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1204Assembly Language Instructions Instruction Set SummayMC = Pllm value+1 ⋅ 131.07 kHz 206Assembly Language Instructions Summay Instruction Set Summay 208Assembly Language Instructions Code Development Tools Introduction MSP50C6xx Software Development Tool MSP50C6xx Software Development ToolCode Development Tools Requirements PC RequirementsDevelopment Requirements RequirementsHardware Installation Hardware InstallationSoftware Installation Software Installation±5. Setup Window ±6. Exit Setup Dialog ±8. Choose Destination Location Dialog ±9. Select Program Folder Dialog ±10. Copying Files ±11.Setup Complete Dialog Open Screen Software EmulatorSoftware Emulator ±13. Project Menu ±15. File Menu Options ProjectsDescription of Windows ±16. MSP50P614/MSP50C614 Code Development Windows±17. RAM Window ±18. CPU Window ±19. Program Window ±20. Hardware Breakpoint Dialog ±21. Inspect Dialog ±23. I/O Ports Window Debugging a Program±24. Debug Menu Software Emulator ±25. Eprom Programming Dialog ±26. Trace Mode Initializing Chip ±27. Init Menu OptionEmulator Options ±28. Options Menu ±30. Windows Menu Options Emulator Online Help System±31. Context Sensitive Help System Known Differences, Incompatibilities, Restrictions Assembler DLL AssemblerAssembler Examples Assembler Directives~ indicates bitwise complement #ELSE see #IF and #IFDEF #IFDEFExample #IFDEF symbol #IFNDEF symbol#ELSE #ENDIFAssembler Linker LinkerIerr=LINKMAIN sourcefile,exefile C± ± Compiler± ± Compiler Foreword External References Variable TypesType Name Mnemonic Range Size in Bytes Example Defines a replacement string for a given string 4 C± ± DirectivesWithout Arguments With ArgumentsSee #if directive Must be present to terminate a #ifdef or #ifndef directiveInclude Files Function Prototypes and Declarations InitializationsRAM Usage String Functions±1. String Functions Constant Functions An example of the use of xferconst isImplementation Details ComparisonsThis section is C± ± specific Signed comparison of a and b. a is in A0, b is in A0~Assembly Vector Unsigned comparison of a and b. a is in A0, b is in A0~Division Function CallsStack frame has the following structure Low Address High AddressProgramming Example Cmmfunc bidonint i1,char *i2 is valid, butOn Call On RETIfteststringm2,0,lgm2,LTSN Programming Example, C ±± With Assembly Routines ±±±±±±±±±±±±±±± Addb R7,2 To C function return in cmmreturn ±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data Param ±±±±±±±±±±±±±± To ASM function return Provided ExternalData Iprtc Implementation Details Nop ret Dummy interrupt routines Implementation Details Implementation Details Reported Bugs With Code Development Tool Beware of Stack CorruptionBeware of Stack Corruption Page Applications Application Circuits Application CircuitsMSP50P614 only 100 kΩ MSP50C614/MSP50P614 Initialization Codes MSP50C614/MSP50P614 Initialization CodesFile init.asm Begloop ~,TIM2REFOSC + TIM2IMR Texas Instruments C614 Synthesis Code OverviewGetting Started Texas Instruments C614 Synthesis CodeRunning the Program Directory StructureSpkram.irx File Description ROMRAM Usage Adding Another ModuleUnderstanding the RAM Map Modifying Files and ProjectsMemory Overlay These files may be edited for special purpose codeThese files should never be edited Creating a New ProjectROM Usage With Respect to Various Synthesis Algorithms ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Die Bond-Out Coordinates Mechanical InformationMechanical Information Package Information Customer Information±1 -Pin PJM Mechanical Information ±2 -Pin Grid Array Package for the Development Device, P614 ±3 Pin Grid Array PGA Package Leads, P614 Customer Information Fields in the ROM Customer Information Fields in the ROMDevice Production Sequence Speech Development CycleSpeech Development Cycle Device Production Sequence NprfOrdering Information New Product Release FormsOrdering Information 614Authorization to Generate MASKS, PROTOTYPES, and Risk Units New Product Release FormsPage Introduction Features Architecture MSP50C605 Preliminary DataArchitecture FeaturesPort Name IO Location MSP50C614 MSP50C605 3 I/O Pins 1 RAM2 ROM Port Description Function Name AddressFigure A±1. MSP50C605 Architecture Program Memory Data MemoryData ROM Peripheral PortsPlastic Package Description Pin# Page Introduction Features Architecture Packaging MSP50C604 Preliminary DataIntroduction Architecture MSP50C604 Preliminary DataFigure B±1. MSP50C604 Block Diagram Host Write Sequence Slave Mode OperationHost Read Sequence Data Memory Program MemoryPeripheral Ports Interrupts Packaging PackagingPlastic Package Packaging MSP50C605 Data Sheet TopicMSP50C605 Data Sheet