MSP50C614 Mixed-Signal Processor Users Guide
Important Notice
This document uses the following conventions
How to Use This Manual
About This Manual
Notational Conventions
Notational Conventions
Csr ±a /user/ti/simuboard/utilities
This provides three choices *, *+, or *±
Information About Cautions and Warnings
Information About Cautions and Warnings
Trademarks
This book may contain cautions and warnings
Page
Contents
Contents
Assembly Language Instructions
Code Development Tools
Contentsix
Customer Information
ROM Usage With Respect to Various Synthesis Algorithms
Applications
Contentsxi
Figures
±13
±10
±11
±12
Tables
±35
±32
±33
±34
Page
Introduction to the MSP50C614
Features of the C614
Features of the C614
Introduction to the MSP50C614
Applications
Applications
Development Device MSP50P614
Development Device MSP50P614
Functional Description
Functional Description
C605 and C604 Preliminary Information
C605 and C604 Preliminary Information
±1. Functional Block Diagram for the C614
Resistor Trim Operation Connections
Crystal Oscillator Operation Connections
±3. Reset Circuit
Terminal Assignments and Signal Descriptions
Terminal Assignments and Signal Descriptions
±1. Signal and Pad Descriptions for the C614
Description Pin #
±2. MSP50C614 100-Pin PJM Plastic Package Pinout Description
PD0 PD1 PD2 PD3 PD4 PD5 PD6
±5 Pin Grid Array Package for the Development Device, P614
VPP VSS VDD DAC M DAC P
MSP50C614 Architecture
Architecture Overview
MSP50C614 Architecture
±1. MSP50C614 Core Processor Block Diagram
ALU
Computation Unit
Computation Unit
Multiplier
±1. Signed and Unsigned Integer Representation
Computation Unit
Arithmetic Logic Unit
±3. Overview of the Multiplier Unit Operation
Accumulator Block
±4. Overview of the Arithmetic Logic Unit
AP0 . . . AP3
Accumulator Block
AC0 . . . AC31
Accumulator Block Pointers
Data Memory Address Unit
Data Memory Address Unit
±6. Data Memory Address Unit
RAM Configuration
Data Memory Addressing Modes
Program Counter Unit
Program Counter Unit
Bit Logic Unit
Memory Organization RAM and ROM
Memory Organization RAM and ROM
Memory Map
Peripheral Communications Ports
±7. C614 Memory Map not drawn to scale
±2. Summary of C614s Peripheral Communications Ports
Reset LOW
Interrupt Name ROM address Event Source Interrupt Priority
Interrupt Vectors
ROM Code Security
Write only
Block Protection Word
= the value programmed at FM5… FM0 false
= the value programmed at TM5… TM0 true
Protection marker
≡ the binary complement of NTM
Interrupt Logic
Interrupt Logic
Macro Call Vectors
IFR
Interrupt Logic
±8. Interrupt Initialization Sequence
Timer Registers
Timer Registers
Triggers INT1 on underflow
Timer Registers
Clock Control
Clock Control
Oscillator Options
PLL Performance
Clock Speed Control Register
±9. PLL Performance
ClkSpdCtrl register
CPU
ClkSpdCtrl Value Copied Shaded
RTO Oscillator Trim Adjustment
Rtrim Register Read Only Applies to MSP50C614 Device Only
Execution Timing
Execution Timing
Reduced Power Modes
Reduced Power Modes
Reduced Power Modes
Reduced Power Modes
Light MID Deep
±3. Programmable Bits Needed to Control Reduced Power Modes
By Controls
→ deeper sleep … relatively less power →
Component Determined
Deeper sleep … Relatively less power → Event Determined
Global interrupt enable is SET
Peripheral Functions
Port a Port B Port C Port D Port E
I/O
General-Purpose I/O Ports
Peripheral Functions
Input Port F
Dedicated Input Port F
Totem-Pole Output Port G
Dedicated Output Port G
Internal and External Interrupts
Branch on D Port
Interrupt Vector Source Trigger Event Priority Comment
±1. Interrupts
Digital-to-Analog Converter DAC
Digital-to-Analog Converter DAC
Pulse-Density Modulation Rate
DAC Control and Data Registers
Overflow bits Least-significant data value Ignored bits
±1. PDM Clock Divider
PDM Clock Divider
Digital-to-Analog Converter DAC
CPU
Pllm
Comparator
Address
For INT7 is enabled
TIMER1 starts counting
Cleared. Refer to .7, Interrupt Logic, for more details
Comparator
IntGenCtrl register
Interrupt/General Control Register
Interrupt/General Control Register
Interrupt/General Control Register
Hardware Initialization States
Hardware Initialization States
Hardware Initialization States
RZF
Bit Bit Name Initialized Value Description
Page
Assembly Language Instructions
System Registers
Introduction
System Registers
Assembly Language Instructions
Top of Stack, TOS
Accumulators AC0±AC31
Product High Register PH
Product Low Register PL
Bit
Accumulator Pointers AP0±AP3
Indirect Register R0±R7
Status Register Stat
String Register STR
Function
±1. Status Register Stat
1 MSP50P614/MSP50C614 Instruction Syntax
Instruction Syntax and Addressing Modes
Next a
±2. Addressing Mode Encoding
Addressing Modes
Opcode
±3. Rx Bit Description
±4. Addressing Mode Bits and adrs Field Description
±6. Auto Increment and Auto Decrement Modes
±5. MSP50P614/MSP50C614 Addressing Modes Summary
Clocks Words Addressing Operation, ² Syntax
Flag addressing mode encoding, flagadrs
Flag Repeat
Flagadrs
Example
Immediate Addressing
Syntax
Mulr *0x02A1
Direct Addressing
MOV *0x012F * 2, *A0
SyntaxOperation
Indirect Addressing
±9. Indirect Addressing Syntax
Movb *R7++, A3
Relative Addressing
MOV A2, *R0
*R4++
Short Relative
A0, *R3+R5
Long Relative
MOV A3, *R6+0x10
XOR TF1, *R6+0x20
Flag Addressing
TF1, *0x20
Or TF2, *R6+0x02
8 Tag/Flag Bits
TF1,*ram1 TF1 bit in Stat is set!?
Possible sources of confusion Consider the following code
Instruction Classification
±10. Symbols and Explanation
Symbol Explanation
Instruction Classification
Class Sub- Description
±11. Symbols and Explanation
±11. Instruction Classification
Class Sub Description
Class 1 Instructions Memory and Accumulator Reference
±12. Classes and Opcode Definition
C1b
±13. Class 1 Instruction Encoding
±14. Class 1a Instruction Description
C1a ~A~
C1b Mnemonic Description
±15. Class 1b Instruction Description
Shltpls a n, adrs
Class 2 Instructions Accumulator and Constant Reference
C2a Mnemonic Description
±16. Class 2 Instruction Encoding
±17. Class 2a Instruction Description
ADD An ~, An ~, imm16 , next a
±18. Class 2b Instruction Description
Class 3 Instruction Accumulator Reference
C2b Mnemonic Description
Mnemonic Description
±19. Class 3 Instruction Encoding
±20. Class 3 Instruction Description
Zero or be set equal to the sign bit Xsgm dependent
MOV SV, An~ , next a
±21. Class 4a Instruction Encoding
Class 4 Instructions Address Register and Memory Reference
±25. Class 4d Instruction Description
±22. Class 4a Instruction Description
±23. Class 4b Instruction Description
±24. Class 4c Instruction Description
±27. Class 5 Instruction Description
Class 5 Instructions Memory Reference
±26. Class 5 Instruction Encoding
RET²
C6a Mnemonic Description
Class 6 Instructions Port and Memory Reference
±28. Class 6a Instruction Encoding
±29. Class 6a Instruction Description
C6b Mnemonic Description
±30. Class 6b Instruction Description
Class 7 Instructions Program Control
Ccc
±31. Class 7 Instruction Encoding and Description
Vector8
Jcc
±32. Class 8a Instruction Encoding
Class 8 Instructions Logic and Bit
C8a Mnemonic Description
±33. Class 8a Instruction Description
±34. Class 8b Instruction Description
Class 9 Instructions Miscellaneous
C9a Mnemonic Description
±35. Class 9a Instruction Encoding
±36. Class 9a Instruction Description
±37. Class 9b Instruction Description
C9c Mnemonic Description
Bit, Byte, Word and String Addressing
±38. Class 9c Instruction Description
±39. Class 9d Instruction Description
±3. Data Memory Organization and Addressing
MOV A0, *0x0004
Mode Address Used Data Order Rx Post modify ²
±40. Data Memory Address and Data Relationship
Movb A0, *0x0003
Which uses the absolute word memory address
±4. Data Memory Example
Rflag
MSP50P614/MSP50C614 Computational Modes
MSP50P614/MSP50C614 Computational Modes
±41. MSP50P614/MSP50C614 Computational Modes
Computational Setting Resetting Function Mode Instruction
SXM
Example 4.6.1 SXM
Example 4.6.1 Sovm
Example 4.6.2 Sovm
Hardware Loop Instructions
Hardware Loop Instructions
Syntax Operation Limitations
±42. Hardware Loops in MSP50P614/MSP50C614
Registers register# = value
String Instructions
±43. Initial Processor State for String Instructions
String Instructions
Mulapl A0, A0~
Instructions Description Data Transfer
Lookup Instructions
±44. Lookup Instructions
Lookup Instructions
MOV An, adrs SUB An MOV An, *An
Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-m
Input/Output Instructions
Special Filter Instructions
Input/Output Instructions
Special Filter Instructions
STR,N±2
STR,0
0x0104
After FIR/COR execution
Important note about setting the Stat register
Firkcoeffs
Coeffarray
Coeffarray address FIRK/CORK only Program memory FIRK/CORK
Coeffarray Samplebuf address
FIR/COR only = 0..N
Samplebuf Coeffarray is stored
Conditionals
Conditionals
≤ port4 ≤ ≤ port6 ≤
Symbol Meaning
Operands
≤ dma6 ≤ ≤ dma16 ≤
Flg
Adrsn
Clk
Dma n
Port n
Offset n
Pma n
±47. Flag Addressing Syntax and BIts
±46. Addressing Mode Bits and adrs Field Description
±45. Auto Increment and Decrement
Individual Instruction Descriptions
Individual Instruction Descriptions
Execution
14.1 ADD Add word
See Also
Description
Opcode
Addb
PC PC + Flags Affected
Clock , clk Words , w
Adds Add String
Adds A1, A1~, A1
14.4 Bitwise
TF2, *0x0020
ANDS, ANDB, OR, ORB, ORS, XOR, XORB, Xors
A3, *R4б
Clock , clk Word , w
Andb Bitwise and Byte
Src byte PC PC +
OF, SF, ZF, CF are set accordingly
Clock, clk Word, w
Ands Bitwise and String
Ands A0, A0~, A0
Ands A0, A0~, *R2
Order to loop N times
Begloop Begin Loop
Save next instruction address PC +
Flags Affected None Opcode
Call Unconditional Subroutine Call
NOP
TOS
TOS PC +
R7 +
True condition Not true condition
±48. Names for cc
Syntax Alternate Syntax Description
Crnbe
CALL, VCALL, RET, Iret
0x2010
CTF1
CMPB, CMPS, Jcc, Ccc
14.10 CMP Compare Two Words
Stat flags set by src ± src1 operation
PC = PC + w
CMP R0, R5
CMP R2, 0xfe20
Cmpb R3
Cmpb Compare Two Bytes
Cmps A2, A2~
Cmps Compare Two Strings
PC PC + w Flags Affected
Cmps A1~
Xeven ++
14.13 COR Correlation Filter Function
3n R+2
Xeven = R xeven + R5
Rxeven = Rxeven + R5
Cork Correlation Filter Function
Sample data. During Cork execution, interrupt is queued
An, *Rx 3nR+2
BEGLOOP, Inte
Endloop End Loop
Decrement R4 by n 1 or First address after Begloop Else
Argument, it assumes n =1
Dest , mod
Extsgn Sign Extend Word
An~ , next a
Copy accumulator sign flag SF to all 16 bits of An~
Extsgns Sign Extend String
Extsgn
2n R+2
14.18 FIR FIR Filter Function Coefficients in RAM
Assembly Language Instructions 101
RPT, FIR, COR, Cork
Firk
Be even. During Firk execution, interrupts are queued
Stop processor clocks
Assembly Language Instructions 103
Idle Halt Processor
A2~, 0x3d
14.21 Input From Port Into Word
INS, OUT, Outs
IN, OUT, Outs
14.22 INS Input From Port Into String
INTE, Iret
Intd Interrupt Disable
IM is Stat bit
Stat to
INTD, Iret
Inte Interrupt Enable
Assembly Language Instructions 107
Return from interrupt. Pop top of stack to program counter
Iret Return From Interrupt
R7 R7 ±
See Also RET, CALL, C cc, INTE, Intd Description
PC PC +
14.26 Jcc Conditional Jumps
110
If test condition is false, a NOP is executed
JIN1 0x2010, R1±±
See Also JMP, CALL, C cc Example
JNZ
JE 0x2010, R3++R5
See Also Jcc, CALL, Ccc Example
14.27 JMP Unconditional Jump
Post±modify Rx if specified
RCF and RZF affected by post±modification of Rx
14.28 MOV Move Data Word From Source to Destination
STR, imm8
XSF, XZF are set accordingly
Clock, clk Word, w With RPT, clk Class
TFn, cc , Rx
116
With some operand types
Example 4.14.28.12 MOV *0x0200 * 2, R0
MOVU, MOVT, MOVB, MOVBS, Movs
Example 4.14.28.10 MOV MR, A3, ±±A
Example 4.14.28.11 MOV A1~, *A1
Example 4.14.28.18 MOV *R6 + 8 * 2, DP
Example 4.14.28.13 MOV R1, 0x0200
Example 4.14.28.15 MOV *0x0200 * 2, R0
Transfer R5 to R0 Example
MOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movaph Move With Adding PH
Execution + PH
MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movaphs Move With Adding PH
Execution An + PH
Background. See .8 for more details
Copy data memory byte pointed by R2 to accumulator A0
Movb Move Byte From Source to Destination
Copy value of unsigned src byte to dest byte
Movb A0, *R2
Movb R2
Movb *R2, A0
Movb A0, 0xf2
Movbs *0x0200, A2
Movbs Move Byte String from Source to Destination
TAG bit is set to bit 17 th value
Movbs A2, *0x0200
Movs Move String from Source to Destination
Movs A1~, A1
Movs A2~
Movs A1, A1~
MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs
Assembly Language Instructions 127
Movsph
MOVSPH, MOVAPH, MOVAPHS, MOVTPH, Movtphs
Second word ± PH MR contents of adrs
Movsphs Move String With Subtract From PH
Details
MOVU, MOV, MOVT, MOVB, MOVBS, Movs
Movt
PC PC + w Flags Affected None Opcode
Available
Copy the value pointed by R3 to MR
Movu Move Data Unsigned
TAG bit is set accordingly UM is set to
MOV, MOVB, MOVT, MOVBS, Movs
Assembly Language Instructions 131
MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl
14.38 MUL Multiply Rounded
MR * src PC PC + w Flags Affected
Accumulator pointer if specified
MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
Length nS+2, where nS is the value in STR register
Muls Multiply String With No Data Transfer
PH,PL MR * src string
MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls
Mulapl Multiply and Accumulate Result
PH ,PL MR * src
Background. See .8 for more detail
MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
Mulapls Multiply String and Accumulate Result
MR * src
Syntax Description Mulspl adrs
Mulspl Multiply and Subtract PL From Accumulator
Occuring in the background. See .8 for more details
MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls
Syntax Description Mulspls adrs
Mulspls Multiply String and Subtract PL From Accumulator
From dest string
MULSPL, MULTPL, MULTPLS, MULAPL, Mulapls
Multpl Multiply and Transfer PL to Accumulator
MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls
Multpls
Execution PH, PL MR * src PC PC + Flags Affected
Stored in An string
Example 4.14.46.1 Negac A3~, A3, ±±A
Negac Twos Complement Negation of Accumulator
Accumulator
NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
Assembly Language Instructions 141
Negacs Twos Complement Negation of Accumulator String
Dest accumulator string
RPT
14.48 NOP No Operation
Execution PC PC +
Example 4.14.49.1 Notac A3~, A3, ±±A
Notac Ones Complement Negation of Accumulator
NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors
NEGAC, Negacs
A3~
Notacs Ones Complement Negation of Accumulator String
Accumulator string
Negacs
Accumulator pointers are allowed with some operand types
14.51 or Bitwise Logical or
TFn bits in Stat register are set accordingly
Or TF1, *R6+0x22
ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
Or A0, *R0++R5
OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
14.52 ORB Bitwise or Byte
Or src
Accumulator is affected
ORS A0, A0~, A0
14.53 ORS Bitwise or String
PC + w Flags Affected
OR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs
OUTS, IN, INS
14.54 OUT
Address is multipled by 4 to get the actual port address
Port6 , An ~
Outs Output String to Port
Port6 specified in the instruction
OUT, IN, INS
CALL, i.e., RET followed by a RET should not be allowed
Assembly Language Instructions 151
14.56 RET Return From Subroutine CALL, Ccc
PC TOS
Example 4.14.57.2 Rflag *R6 +
Rflag Reset Memory Flag
Sflag , Stag , Rtag
STAT.FM
Reset Fractional Mode Syntax
Resets the fractional mode. Clears FM bit of Stat
14.58 RFM
Stat .OM
Rovm Reset Overflow Mode
Saturation output normal mode
Resets the overflow mode to zero
After execution completes
14.60 RPT Repeat Next Instruction
Load src to repeat counter
Load imm8 to repeat counter
Rtag *R6+0x0003
Rtag Reset Tag
Stag , Rflag , Sflag
Rtag *R6+0x0002
SXM
14.62 RXM Reset Extended Sign Mode
Assembly Language Instructions 157
STAT.XM
Rflag , Stag , Rtag
Address flagadrs only accesses the 17 th bit
Sflag Set Memory Flag
Set fractional mode. Set FM bit of Stat to
14.64 SFM Set Fractional Mode
Mode for signed fractional arithmetic
Assembly Language Instructions 159
Shls
14.65 SHL Shift Left
PH , PL
Accumulator. Use Shlac for this purpose
Example 4.14.66.2 Shlac A1~, A1, ±±A
Shlac Shift Left Accumulator
Its offset. LSB of result is set to zero
Shift accumulator A1 by one bit to the left
Accumulators in the string
Shlacs Shift Left Accumulator String Individually
Example 4.14.68.3 Shlapl A1, A1, ++A
Shlapl Shift Left with Accumulate
Example 4.14.68.1 Shlapl A0, *R4++R5
Shlapl A2, *R1++
Shift a n ~ string left, addb PL to a n ~
Shlapls Shift Left String With Accumulate
Shift data memory string left, add PL to a n
An~
Assembly Language Instructions 165
Shls Shift Left Accumulator String to Product
Execution PH, PL
Example 4.14.71.3 Shlspl A1, A1, ++A
Shlspl Shift Left With Subtract PL
Example 4.14.71.1 Shlspl A0, *R4++R5
Shlspl A2, *R1++
Syntax Description Shlspls An, adrs
Shlspls Shift Left String With Subtract PL
Bit to the next accumulator
Shlspl , Shltpl , SHLTPLS, SHLAPL, Shlapls
Example 4.14.73.3 Shltpl A1, A1, ++A
Shltpl Shift Left and Transfer PL to Accumulator
Example 4.14.73.1 Shltpl A0, *R4++R5
Shltpl A2, *R1++
SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls
Shltpls Shift Left String and Transfer PL to Accumulator
Execution PH, PL src SV
Receives the same data as PH
Example 4.14.75.2 Shrac A1~, A1, ++A
Shrac Shift Accumulator Right
Register
Shift right one bit the accumulator A1
Shltpls
Assembly Language Instructions 171
Shracs Shift Accumulator String Right
SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl
STAT.OM
Set Overflow Mode Syntax
Output DSP mode
Sovm
Stag *0x401
Stag
RTAG, RFLAG, Sflag
An ~ , An ~ , imm16 , next a
14.79 SUB Subtract
Dest, src , src1 , next a
An ~ , An , adrs , next a
SUB R3, R5
Example 4.14.79.2 SUB A0, A0, 2, ++A
SUB A1, A1~, A1
SUB A3~, A3, *R4Ð
Syntax Description Subb a n, imm8
Subb Subtract Byte
Subtract 0x45 from accumulator A2 byte
Subtract 0xF2 from register R3 byte
Subs Subtract Accumulataor String
Assembly Language Instructions 177
Subs A3~, A3~, PH
Subs A2, A2, A2~
Subs A2, A2~, A2
RXM
14.82 SXM Set Extended Sign Mode
Sets extended sign mode status register Stat bit 0 to
Assembly Language Instructions 179
See Also RET, IRET, CALL, C cc Example
Vcall Vectored Call
Push PC + 0x7F00
R7 R7 + Flags Affected
TAG bit is set accordingly Src is flagadrs
14.84 XOR Logical XOR
XOR src For two operands
XOR src For three operands
Example 4.14.84.2 XOR A0, A0, 2, ++A
XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Example 4.14.84.1 XOR A1, A1, 0x13FF
XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Assembly Language Instructions 183
Xorb Logical XOR Byte
Xors A2, A2~, A2
Xors Logical XOR String
Dest string
XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Zacs
Reset the content of accumulator A0 to zero
Assembly Language Instructions 185
14.87 ZAC Zero Accumulator
Zero the specified accumulator string
Reset the content of offset accumulator string A1~ to zero
Zacs Zero Accumulator String
PC PC + Flags Affected ZF =
Instruction Set Encoding
Assembly Language Instructions 187
Instruction Set Encoding
188
Assembly Language Instructions 189
190
Assembly Language Instructions 191
192
Assembly Language Instructions 193
194
True condition Not true condition
Assembly Language Instructions 195
Instruction Set Summary
Rx, R5
Pma16 , Rmod Assembly Language Instructions 197
An~, An~ , next a
An~, imm16 , next a
An ~, imm16 , next a
Adrs, a n~ , next a ±46
~, adrs , next a ±46
Adrs , *An ±46
Adrs, TOS
Assembly Language Instructions 199
Adrs, SV
Adrs, APn
~ , a n~
MR, adrs
~ , next a
~, a n~ , next a
An~, An~, An
An~, An~ , next a NR+3 Assembly Language Instructions 201
TFn, flagadrs NR+3 TFn, cc , Rx
An~, An~, pma16
~, a n~, PH
~, a n~
~, a n, a n~ , next a
~, a n, a n~
Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1
Conditional on RCF=1 Not condition RCF=0
Conditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1
Conditional on RZF=1 Not condition RZF=0
Instruction Set Summay
204Assembly Language Instructions
MC = Pllm value+1 ⋅ 131.07 kHz
206Assembly Language Instructions
Summay
Instruction Set Summay 208Assembly Language Instructions
Code Development Tools
Introduction
Code Development Tools
MSP50C6xx Software Development Tool
MSP50C6xx Software Development Tool
Requirements
Requirements
PC Requirements
Development Requirements
Hardware Installation
Hardware Installation
Software Installation
Software Installation
±5. Setup Window
±6. Exit Setup Dialog
±8. Choose Destination Location Dialog
±9. Select Program Folder Dialog
±10. Copying Files
±11.Setup Complete Dialog
Software Emulator
Software Emulator
Open Screen
±13. Project Menu
Projects
±15. File Menu Options
±16. MSP50P614/MSP50C614 Code Development Windows
Description of Windows
±17. RAM Window
±18. CPU Window
±19. Program Window
±20. Hardware Breakpoint Dialog
±21. Inspect Dialog
Debugging a Program
±23. I/O Ports Window
±24. Debug Menu
Software Emulator
±25. Eprom Programming Dialog
±26. Trace Mode
±27. Init Menu Option
Initializing Chip
Emulator Options
±28. Options Menu
Emulator Online Help System
±30. Windows Menu Options
±31. Context Sensitive Help System
Known Differences, Incompatibilities, Restrictions
Assembler
Assembler
Assembler DLL
~ indicates bitwise complement
Assembler Directives
Examples
#IFDEF
#ELSE see #IF and #IFDEF
#ENDIF
Example #IFDEF symbol
#IFNDEF symbol
#ELSE
Assembler
Linker
Linker
± ± Compiler
C± ± Compiler
Ierr=LINKMAIN sourcefile,exefile
Foreword
Type Name Mnemonic Range Size in Bytes Example
Variable Types
External References
With Arguments
Defines a replacement string for a given string
4 C± ± Directives
Without Arguments
Must be present to terminate a #ifdef or #ifndef directive
See #if directive
Include Files
String Functions
Function Prototypes and Declarations
Initializations
RAM Usage
±1. String Functions
An example of the use of xferconst is
Constant Functions
Signed comparison of a and b. a is in A0, b is in A0~
Implementation Details
Comparisons
This section is C± ± specific
Unsigned comparison of a and b. a is in A0, b is in A0~
Assembly Vector
Low Address High Address
Division
Function Calls
Stack frame has the following structure
On RET
Programming Example
Cmmfunc bidonint i1,char *i2 is valid, but
On Call
Ifteststringm2,0,lgm2,LTSN
Programming Example, C ±± With Assembly Routines
±±±±±±±±±±±±±±±
Addb R7,2
To C function return in cmmreturn
±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data
Param ±±±±±±±±±±±±±±
To ASM function return
External
Provided
Data
Iprtc
Implementation Details
Nop ret Dummy interrupt routines
Implementation Details
Implementation Details
Beware of Stack Corruption
Beware of Stack Corruption
Reported Bugs With Code Development Tool
Page
Applications
Application Circuits
Application Circuits
MSP50P614 only 100 kΩ
MSP50C614/MSP50P614 Initialization Codes
MSP50C614/MSP50P614 Initialization Codes
File init.asm
Begloop
~,TIM2REFOSC + TIM2IMR
Texas Instruments C614 Synthesis Code
Texas Instruments C614 Synthesis Code
Overview
Getting Started
Directory Structure
Running the Program
Spkram.irx
ROM
File Description
Modifying Files and Projects
RAM Usage
Adding Another Module
Understanding the RAM Map
Creating a New Project
Memory Overlay
These files may be edited for special purpose code
These files should never be edited
ROM Usage With Respect to Various Synthesis Algorithms
ROM Usage With Respect to Various Synthesis Algorithms
Customer Information
Mechanical Information
Mechanical Information
Die Bond-Out Coordinates
Customer Information
Package Information
±1 -Pin PJM Mechanical Information
±2 -Pin Grid Array Package for the Development Device, P614
±3 Pin Grid Array PGA Package Leads, P614
Customer Information Fields in the ROM
Customer Information Fields in the ROM
Speech Development Cycle
Speech Development Cycle
Device Production Sequence
Nprf
Device Production Sequence
614
Ordering Information
New Product Release Forms
Ordering Information
New Product Release Forms
Authorization to Generate MASKS, PROTOTYPES, and Risk Units
Page
MSP50C605 Preliminary Data
Introduction Features Architecture
Port Name IO Location MSP50C614 MSP50C605
Features
Architecture
Port Description Function Name Address
3 I/O Pins
1 RAM
2 ROM
Figure A±1. MSP50C605 Architecture
Peripheral Ports
Program Memory
Data Memory
Data ROM
Plastic Package
Description Pin#
Page
MSP50C604 Preliminary Data
Introduction Features Architecture Packaging
Introduction
MSP50C604 Preliminary Data
Figure B±1. MSP50C604 Block Diagram
Host Read Sequence
Slave Mode Operation
Host Write Sequence
Peripheral Ports
Program Memory
Data Memory
Interrupts
Packaging
Packaging
Plastic Package
Packaging
Topic
MSP50C605 Data Sheet
MSP50C605 Data Sheet
