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Texas Instruments MSP50C614 manual Cpu

Models: MSP50C614

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Digital-to-Analog Converter (DAC)

8 kHz Nominal Synthesis Rate

32.768 kHz Oscillator Reference

			ClkSpdCtrl					Number of	Number of
			PLLM	Master		CPU	Output	Instructs	Instructs
	IntGenCtrl	Over-	Register	Clock	PDM	Clock	Sampling	Between	Between
DAC	PDMCD	Sampling	Value	Rate	Rate	Rate	Rate	DAC	8 kHz
Precision	Bit	Factor	(hex)	(MHz)	(MHz)	(MHz)	(kHz)	Interrupts	Interrupts

8 bits	1	1x	0x 0F	2.10	2.10	1.05	8.19	128	128
		2x	0x 1E	4.06	4.06	2.03	15.87	128	256
		4x	0x 3E	8.26	8.26	4.13	32.26	128	512
		8x	0x 7C	16.38	16.38	8.19	64.00	128	1024

	0	1x	0x 1E	4.06	2.03	2.03	7.94	256	256
		2x	0x 3E	8.26	4.13	4.13	16.13	256	512
		4x	0x 7C	16.38	8.19	8.19	32.00	256	1024

9 bits	1	1x	0x 1E	4.06	4.06	2.03	7.94	256	256
		2x	0x 3E	8.26	8.26	4.13	16.13	256	512
		4x	0x 7C	16.38	16.38	8.19	32.00	256	1024

	0	1x	0x 3E	8.26	4.13	4.13	8.06	512	512
		2x	0x 7C	16.38	8.19	8.19	16.00	512	1024

10 bits	1	1x	0x 3E	8.26	8.26	4.13	8.06	512	512
		2x	0x 7C	16.38	16.38	8.19	16.00	512	1024

	0	1x	0x 7C	16.38	8.19	8.19	8.00	1024	1024

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Image 82

Texas Instruments MSP50C614 manual Cpu

Contents

MSP50C614 Mixed-Signal Processor Users Guide Important Notice Notational Conventions How to Use This ManualAbout This Manual This document uses the following conventionsThis provides three choices *, *+, or *± Csr ±a /user/ti/simuboard/utilitiesNotational Conventions This book may contain cautions and warnings Information About Cautions and WarningsTrademarks Information About Cautions and WarningsPage Contents Assembly Language Instructions ContentsContentsix Code Development ToolsApplications ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Contentsxi Figures ±12 ±10±11 ±13Tables ±34 ±32±33 ±35Page Introduction to the MSP50C614 Features of the C614 Features of the C614Applications ApplicationsIntroduction to the MSP50C614 Development Device MSP50P614 Development Device MSP50P614Functional Description Functional DescriptionC605 and C604 Preliminary Information C605 and C604 Preliminary Information±1. Functional Block Diagram for the C614 Crystal Oscillator Operation Connections Resistor Trim Operation Connections±3. Reset Circuit ±1. Signal and Pad Descriptions for the C614 Terminal Assignments and Signal DescriptionsTerminal Assignments and Signal Descriptions ±2. MSP50C614 100-Pin PJM Plastic Package Pinout Description Description Pin #PD0 PD1 PD2 PD3 PD4 PD5 PD6 ±5 Pin Grid Array Package for the Development Device, P614 VPP VSS VDD DAC M DAC P MSP50C614 Architecture Architecture Overview ±1. MSP50C614 Core Processor Block Diagram MSP50C614 ArchitectureALU ±1. Signed and Unsigned Integer Representation Computation UnitMultiplier Computation UnitComputation Unit ±3. Overview of the Multiplier Unit Operation Arithmetic Logic UnitAccumulator Block ±4. Overview of the Arithmetic Logic Unit Accumulator Block Pointers Accumulator BlockAC0 . . . AC31 AP0 . . . AP3Data Memory Address Unit Data Memory Address UnitRAM Configuration ±6. Data Memory Address UnitData Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM ±7. C614 Memory Map not drawn to scale Peripheral Communications PortsReset LOW ±2. Summary of C614s Peripheral Communications PortsInterrupt Vectors Interrupt Name ROM address Event Source Interrupt PriorityROM Code Security Block Protection Word Write only≡ the binary complement of NTM = the value programmed at TM5… TM0 trueProtection marker = the value programmed at FM5… FM0 falseMacro Call Vectors Interrupt LogicInterrupt Logic IFR Interrupt Logic ±8. Interrupt Initialization Sequence Timer Registers Timer RegistersTriggers INT1 on underflow Timer Registers PLL Performance Clock ControlOscillator Options Clock Control±9. PLL Performance Clock Speed Control RegisterCPU ClkSpdCtrl registerRtrim Register Read Only Applies to MSP50C614 Device Only RTO Oscillator Trim AdjustmentClkSpdCtrl Value Copied Shaded Execution Timing Execution TimingReduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes ±3. Programmable Bits Needed to Control Reduced Power Modes Light MID DeepComponent Determined → deeper sleep … relatively less power →By Controls Deeper sleep … Relatively less power → Event Determined Global interrupt enable is SET Peripheral Functions General-Purpose I/O Ports I/OPort a Port B Port C Port D Port E Peripheral Functions Dedicated Input Port F Input Port FDedicated Output Port G Totem-Pole Output Port GBranch on D Port Internal and External Interrupts±1. Interrupts Interrupt Vector Source Trigger Event Priority CommentDAC Control and Data Registers Digital-to-Analog Converter DACPulse-Density Modulation Rate Digital-to-Analog Converter DACOverflow bits Least-significant data value Ignored bits PDM Clock Divider ±1. PDM Clock DividerDigital-to-Analog Converter DAC CPU Pllm Comparator Cleared. Refer to .7, Interrupt Logic, for more details For INT7 is enabledTIMER1 starts counting AddressComparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Interrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States Bit Bit Name Initialized Value Description RZFPage Assembly Language Instructions Introduction System RegistersTop of Stack, TOS Assembly Language InstructionsSystem Registers Product Low Register PL Product High Register PHAccumulators AC0±AC31 Indirect Register R0±R7 Accumulator Pointers AP0±AP3Bit String Register STR Status Register Stat±1. Status Register Stat FunctionInstruction Syntax and Addressing Modes 1 MSP50P614/MSP50C614 Instruction SyntaxOpcode ±2. Addressing Mode EncodingAddressing Modes Next a±4. Addressing Mode Bits and adrs Field Description ±3. Rx Bit Description±5. MSP50P614/MSP50C614 Addressing Modes Summary ±6. Auto Increment and Auto Decrement ModesFlagadrs Flag addressing mode encoding, flagadrsFlag Repeat Clocks Words Addressing Operation, ² SyntaxSyntax Immediate AddressingExample MOV *0x012F * 2, *A0 Direct AddressingMulr *0x02A1 ±9. Indirect Addressing Syntax Indirect AddressingSyntaxOperation *R4++ Relative AddressingMOV A2, *R0 Movb *R7++, A3A0, *R3+R5 Short RelativeMOV A3, *R6+0x10 Long RelativeOr TF2, *R6+0x02 Flag AddressingTF1, *0x20 XOR TF1, *R6+0x208 Tag/Flag Bits Possible sources of confusion Consider the following code TF1,*ram1 TF1 bit in Stat is set!?Instruction Classification ±10. Symbols and ExplanationSymbol Explanation Instruction Classification±11. Instruction Classification ±11. Symbols and ExplanationClass Sub- Description Class Sub Description ±12. Classes and Opcode Definition Class 1 Instructions Memory and Accumulator ReferenceC1a ~A~ ±13. Class 1 Instruction Encoding±14. Class 1a Instruction Description C1b±15. Class 1b Instruction Description C1b Mnemonic DescriptionClass 2 Instructions Accumulator and Constant Reference Shltpls a n, adrs±17. Class 2a Instruction Description ±16. Class 2 Instruction EncodingC2a Mnemonic Description C2b Mnemonic Description ±18. Class 2b Instruction DescriptionClass 3 Instruction Accumulator Reference ADD An ~, An ~, imm16 , next a±20. Class 3 Instruction Description ±19. Class 3 Instruction EncodingMnemonic Description Zero or be set equal to the sign bit Xsgm dependent MOV SV, An~ , next a Class 4 Instructions Address Register and Memory Reference ±21. Class 4a Instruction Encoding±24. Class 4c Instruction Description ±22. Class 4a Instruction Description±23. Class 4b Instruction Description ±25. Class 4d Instruction Description±26. Class 5 Instruction Encoding Class 5 Instructions Memory Reference±27. Class 5 Instruction Description RET² ±29. Class 6a Instruction Description Class 6 Instructions Port and Memory Reference±28. Class 6a Instruction Encoding C6a Mnemonic DescriptionClass 7 Instructions Program Control ±30. Class 6b Instruction DescriptionC6b Mnemonic Description Jcc ±31. Class 7 Instruction Encoding and DescriptionVector8 CccClass 8 Instructions Logic and Bit ±32. Class 8a Instruction EncodingClass 9 Instructions Miscellaneous ±33. Class 8a Instruction Description±34. Class 8b Instruction Description C8a Mnemonic Description±37. Class 9b Instruction Description ±35. Class 9a Instruction Encoding±36. Class 9a Instruction Description C9a Mnemonic Description±39. Class 9d Instruction Description Bit, Byte, Word and String Addressing±38. Class 9c Instruction Description C9c Mnemonic Description±3. Data Memory Organization and Addressing Movb A0, *0x0003 Mode Address Used Data Order Rx Post modify ²±40. Data Memory Address and Data Relationship MOV A0, *0x0004±4. Data Memory Example Which uses the absolute word memory addressRflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational ModesComputational Setting Resetting Function Mode Instruction ±41. MSP50P614/MSP50C614 Computational ModesSXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop Instructions±42. Hardware Loops in MSP50P614/MSP50C614 Syntax Operation LimitationsString Instructions String Instructions±43. Initial Processor State for String Instructions Registers register# = valueMulapl A0, A0~ Lookup Instructions Lookup Instructions±44. Lookup Instructions Instructions Description Data TransferMOV An, adrs SUB An MOV An, *An Input/Output Instructions Input/Output InstructionsSpecial Filter Instructions Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-mSpecial Filter Instructions STR,N±2 STR,0 0x0104 After FIR/COR execution Important note about setting the Stat register Firkcoeffs FIR/COR only = 0..N Coeffarray address FIRK/CORK only Program memory FIRK/CORKCoeffarray Samplebuf address CoeffarraySamplebuf Coeffarray is stored Conditionals Conditionals≤ dma6 ≤ ≤ dma16 ≤ Symbol MeaningOperands ≤ port4 ≤ ≤ port6 ≤Dma n AdrsnClk FlgPma n Offset nPort n ±45. Auto Increment and Decrement ±46. Addressing Mode Bits and adrs Field Description±47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions14.1 ADD Add word ExecutionDescription See AlsoPC PC + Flags Affected AddbOpcode Adds Add String Clock , clk Words , wAdds A1, A1~, A1 14.4 Bitwise A3, *R4Ð± ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 OF, SF, ZF, CF are set accordingly Andb Bitwise and ByteSrc byte PC PC + Clock , clk Word , wAnds A0, A0~, *R2 Ands Bitwise and StringAnds A0, A0~, A0 Clock, clk Word, wFlags Affected None Opcode Begloop Begin LoopSave next instruction address PC + Order to loop N timesCall Unconditional Subroutine Call R7 + TOSTOS PC + NOP±48. Names for cc True condition Not true conditionSyntax Alternate Syntax Description CTF1 CALL, VCALL, RET, Iret0x2010 CrnbePC = PC + w 14.10 CMP Compare Two WordsStat flags set by src ± src1 operation CMPB, CMPS, Jcc, CccCMP R2, 0xfe20 CMP R0, R5Cmpb Compare Two Bytes Cmpb R3Cmps A1~ Cmps Compare Two StringsPC PC + w Flags Affected Cmps A2, A2~Xeven = R xeven + R5 14.13 COR Correlation Filter Function3n R+2 Xeven ++An, *Rx 3nR+2 Cork Correlation Filter FunctionSample data. During Cork execution, interrupt is queued Rxeven = Rxeven + R5Argument, it assumes n =1 Endloop End LoopDecrement R4 by n 1 or First address after Begloop Else BEGLOOP, InteCopy accumulator sign flag SF to all 16 bits of An~ Extsgn Sign Extend WordAn~ , next a Dest , modExtsgns Sign Extend String DestExtsgn 14.18 FIR FIR Filter Function Coefficients in RAM 2n R+2Assembly Language Instructions 101 Be even. During Firk execution, interrupts are queued FirkRPT, FIR, COR, Cork Idle Halt Processor Assembly Language Instructions 103Stop processor clocks INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d 14.22 INS Input From Port Into String IN, OUT, OutsStat to Intd Interrupt DisableIM is Stat bit INTE, IretAssembly Language Instructions 107 Inte Interrupt EnableINTD, Iret See Also RET, CALL, C cc, INTE, Intd Description Iret Return From InterruptR7 R7 ± Return from interrupt. Pop top of stack to program counter14.26 Jcc Conditional Jumps PC PC +110 If test condition is false, a NOP is executed JE 0x2010, R3++R5 See Also JMP, CALL, C cc ExampleJNZ JIN1 0x2010, R1±±RCF and RZF affected by post±modification of Rx 14.27 JMP Unconditional JumpPost±modify Rx if specified See Also Jcc, CALL, Ccc Example14.28 MOV Move Data Word From Source to Destination TFn, cc , Rx XSF, XZF are set accordinglyClock, clk Word, w With RPT, clk Class STR, imm8116 With some operand types Example 4.14.28.11 MOV A1~, *A1 MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.10 MOV MR, A3, ±±A Example 4.14.28.12 MOV *0x0200 * 2, R0Transfer R5 to R0 Example Example 4.14.28.13 MOV R1, 0x0200Example 4.14.28.15 MOV *0x0200 * 2, R0 Example 4.14.28.18 MOV *R6 + 8 * 2, DPExecution + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Background. See .8 for more details Movaphs Move With Adding PHExecution An + PH MOVAPH, MOVTPH, MOVTPHS, MOVSPH, MovsphsMovb A0, *R2 Movb Move Byte From Source to DestinationCopy value of unsigned src byte to dest byte Copy data memory byte pointed by R2 to accumulator A0Movb A0, 0xf2 Movb *R2, A0Movb R2 Movbs A2, *0x0200 Movbs Move Byte String from Source to DestinationTAG bit is set to bit 17 th value Movbs *0x0200, A2Movs Move String from Source to Destination Movs A1, A1~ Movs A2~Movs A1~, A1 Movsph Assembly Language Instructions 127MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Details Second word ± PH MR contents of adrsMovsphs Move String With Subtract From PH MOVSPH, MOVAPH, MOVAPHS, MOVTPH, MovtphsAvailable MovtPC PC + w Flags Affected None Opcode MOVU, MOV, MOVT, MOVB, MOVBS, MovsMOV, MOVB, MOVT, MOVBS, Movs Movu Move Data UnsignedTAG bit is set accordingly UM is set to Copy the value pointed by R3 to MRAssembly Language Instructions 131 Accumulator pointer if specified 14.38 MUL Multiply RoundedMR * src PC PC + w Flags Affected MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MulaplPH,PL MR * src string Length nS+2, where nS is the value in STR registerMuls Multiply String With No Data Transfer MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MultplsBackground. See .8 for more detail Mulapl Multiply and Accumulate ResultPH ,PL MR * src MULAPLS, MULSPL, MULSPLS, MULTPL, MultplsMR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Mulspl Multiply and Subtract PL From AccumulatorOccuring in the background. See .8 for more details Syntax Description Mulspl adrsMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Mulspls Multiply String and Subtract PL From AccumulatorFrom dest string Syntax Description Mulspls adrsMultpl Multiply and Transfer PL to Accumulator Stored in An string MultplsExecution PH, PL MR * src PC PC + Flags Affected MULTPL, MULAPL, MULAPLS, MULSPL, MulsplsNEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Negac Twos Complement Negation of AccumulatorAccumulator Example 4.14.46.1 Negac A3~, A3, ±±ADest accumulator string Assembly Language Instructions 141Negacs Twos Complement Negation of Accumulator String NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NotacsExecution PC PC + 14.48 NOP No OperationRPT NEGAC, Negacs Notac Ones Complement Negation of AccumulatorNOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors Example 4.14.49.1 Notac A3~, A3, ±±ANegacs Notacs Ones Complement Negation of Accumulator StringAccumulator string A3~TFn bits in Stat register are set accordingly 14.51 or Bitwise Logical orAccumulator pointers are allowed with some operand types Or A0, *R0++R5 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr TF1, *R6+0x22 Accumulator is affected 14.52 ORB Bitwise or ByteOr src OR, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.53 ORS Bitwise or StringPC + w Flags Affected ORS A0, A0~, A0Address is multipled by 4 to get the actual port address 14.54 OUTOUTS, IN, INS OUT, IN, INS Outs Output String to PortPort6 specified in the instruction Port6 , An ~PC TOS Assembly Language Instructions 15114.56 RET Return From Subroutine CALL, Ccc CALL, i.e., RET followed by a RET should not be allowedSflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.57.2 Rflag *R6 + 14.58 RFM Reset Fractional Mode SyntaxResets the fractional mode. Clears FM bit of Stat STAT.FMResets the overflow mode to zero Rovm Reset Overflow ModeSaturation output normal mode Stat .OMLoad imm8 to repeat counter 14.60 RPT Repeat Next InstructionLoad src to repeat counter After execution completesRtag *R6+0x0002 Rtag Reset TagStag , Rflag , Sflag Rtag *R6+0x0003STAT.XM 14.62 RXM Reset Extended Sign ModeAssembly Language Instructions 157 SXMSflag Set Memory Flag Address flagadrs only accesses the 17 th bitRflag , Stag , Rtag Assembly Language Instructions 159 14.64 SFM Set Fractional ModeMode for signed fractional arithmetic Set fractional mode. Set FM bit of Stat toAccumulator. Use Shlac for this purpose 14.65 SHL Shift LeftPH , PL ShlsShift accumulator A1 by one bit to the left Shlac Shift Left AccumulatorIts offset. LSB of result is set to zero Example 4.14.66.2 Shlac A1~, A1, ±±AShlacs Shift Left Accumulator String Individually Accumulators in the stringShlapl A2, *R1++ Shlapl Shift Left with AccumulateExample 4.14.68.1 Shlapl A0, *R4++R5 Example 4.14.68.3 Shlapl A1, A1, ++AShift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ Execution PH, PL Assembly Language Instructions 165Shls Shift Left Accumulator String to Product An~Shlspl A2, *R1++ Shlspl Shift Left With Subtract PLExample 4.14.71.1 Shlspl A0, *R4++R5 Example 4.14.71.3 Shlspl A1, A1, ++AShlspl , Shltpl , SHLTPLS, SHLAPL, Shlapls Shlspls Shift Left String With Subtract PLBit to the next accumulator Syntax Description Shlspls An, adrsShltpl A2, *R1++ Shltpl Shift Left and Transfer PL to AccumulatorExample 4.14.73.1 Shltpl A0, *R4++R5 Example 4.14.73.3 Shltpl A1, A1, ++AReceives the same data as PH Shltpls Shift Left String and Transfer PL to AccumulatorExecution PH, PL src SV SHLTPL, SHLAPL, SHLAPLS, SHLSPL, ShlsplsShift right one bit the accumulator A1 Shrac Shift Accumulator RightRegister Example 4.14.75.2 Shrac A1~, A1, ++ASHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl Assembly Language Instructions 171Shracs Shift Accumulator String Right ShltplsSovm Set Overflow Mode SyntaxOutput DSP mode STAT.OMRTAG, RFLAG, Sflag StagStag *0x401 An ~ , An , adrs , next a 14.79 SUB SubtractDest, src , src1 , next a An ~ , An ~ , imm16 , next aSUB A3~, A3, *R4Ð Example 4.14.79.2 SUB A0, A0, 2, ++ASUB A1, A1~, A1 SUB R3, R5Subtract 0xF2 from register R3 byte Subb Subtract ByteSubtract 0x45 from accumulator A2 byte Syntax Description Subb a n, imm8Assembly Language Instructions 177 Subs Subtract Accumulataor StringSubs A2, A2~, A2 Subs A2, A2, A2~Subs A3~, A3~, PH Assembly Language Instructions 179 14.82 SXM Set Extended Sign ModeSets extended sign mode status register Stat bit 0 to RXMR7 R7 + Flags Affected Vcall Vectored CallPush PC + 0x7F00 See Also RET, IRET, CALL, C cc ExampleXOR src For three operands 14.84 XOR Logical XORXOR src For two operands TAG bit is set accordingly Src is flagadrsExample 4.14.84.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.84.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 183XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors Logical XOR StringDest string Xors A2, A2~, A214.87 ZAC Zero Accumulator Reset the content of accumulator A0 to zeroAssembly Language Instructions 185 ZacsPC PC + Flags Affected ZF = Reset the content of offset accumulator string A1~ to zeroZacs Zero Accumulator String Zero the specified accumulator stringInstruction Set Encoding Assembly Language Instructions 187Instruction Set Encoding 188 Assembly Language Instructions 189 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 True condition Not true conditionInstruction Set Summary An~, imm16 , next a Pma16 , Rmod Assembly Language Instructions 197An~, An~ , next a Rx, R5Adrs , *An ±46 Adrs, a n~ , next a ±46~, adrs , next a ±46 An ~, imm16 , next aAdrs, APn Assembly Language Instructions 199Adrs, SV Adrs, TOS~, a n~ , next a MR, adrs~ , next a ~ , a n~An~, An~, pma16 An~, An~ , next a NR+3 Assembly Language Instructions 201TFn, flagadrs NR+3 TFn, cc , Rx An~, An~, An~, a n, a n~ ~, a n~~, a n, a n~ , next a ~, a n~, PHConditional on RZF=1 Not condition RZF=0 Conditional on RCF=1 Not condition RCF=0Conditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1 Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1204Assembly Language Instructions Instruction Set SummayMC = Pllm value+1 ⋅ 131.07 kHz 206Assembly Language Instructions Summay Instruction Set Summay 208Assembly Language Instructions Code Development Tools Introduction MSP50C6xx Software Development Tool MSP50C6xx Software Development ToolCode Development Tools Development Requirements RequirementsPC Requirements RequirementsHardware Installation Hardware InstallationSoftware Installation Software Installation±5. Setup Window ±6. Exit Setup Dialog ±8. Choose Destination Location Dialog ±9. Select Program Folder Dialog ±10. Copying Files ±11.Setup Complete Dialog Open Screen Software EmulatorSoftware Emulator ±13. Project Menu ±15. File Menu Options ProjectsDescription of Windows ±16. MSP50P614/MSP50C614 Code Development Windows±17. RAM Window ±18. CPU Window ±19. Program Window ±20. Hardware Breakpoint Dialog ±21. Inspect Dialog ±23. I/O Ports Window Debugging a Program±24. Debug Menu Software Emulator ±25. Eprom Programming Dialog ±26. Trace Mode Initializing Chip ±27. Init Menu OptionEmulator Options ±28. Options Menu ±30. Windows Menu Options Emulator Online Help System±31. Context Sensitive Help System Known Differences, Incompatibilities, Restrictions Assembler DLL AssemblerAssembler Examples Assembler Directives~ indicates bitwise complement #ELSE see #IF and #IFDEF #IFDEF#ELSE Example #IFDEF symbol#IFNDEF symbol #ENDIFAssembler Linker LinkerIerr=LINKMAIN sourcefile,exefile C± ± Compiler± ± Compiler Foreword External References Variable TypesType Name Mnemonic Range Size in Bytes Example Without Arguments Defines a replacement string for a given string4 C± ± Directives With ArgumentsSee #if directive Must be present to terminate a #ifdef or #ifndef directiveInclude Files RAM Usage Function Prototypes and DeclarationsInitializations String Functions±1. String Functions Constant Functions An example of the use of xferconst isThis section is C± ± specific Implementation DetailsComparisons Signed comparison of a and b. a is in A0, b is in A0~Assembly Vector Unsigned comparison of a and b. a is in A0, b is in A0~Stack frame has the following structure DivisionFunction Calls Low Address High AddressOn Call Programming ExampleCmmfunc bidonint i1,char *i2 is valid, but On RETIfteststringm2,0,lgm2,LTSN Programming Example, C ±± With Assembly Routines ±±±±±±±±±±±±±±± Addb R7,2 To C function return in cmmreturn ±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data Param ±±±±±±±±±±±±±± To ASM function return Provided ExternalData Iprtc Implementation Details Nop ret Dummy interrupt routines Implementation Details Implementation Details Reported Bugs With Code Development Tool Beware of Stack CorruptionBeware of Stack Corruption Page Applications Application Circuits Application CircuitsMSP50P614 only 100 kΩ MSP50C614/MSP50P614 Initialization Codes MSP50C614/MSP50P614 Initialization CodesFile init.asm Begloop ~,TIM2REFOSC + TIM2IMR Getting Started Texas Instruments C614 Synthesis CodeOverview Texas Instruments C614 Synthesis CodeRunning the Program Directory StructureSpkram.irx File Description ROMUnderstanding the RAM Map RAM UsageAdding Another Module Modifying Files and ProjectsThese files should never be edited Memory OverlayThese files may be edited for special purpose code Creating a New ProjectROM Usage With Respect to Various Synthesis Algorithms ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Die Bond-Out Coordinates Mechanical InformationMechanical Information Package Information Customer Information±1 -Pin PJM Mechanical Information ±2 -Pin Grid Array Package for the Development Device, P614 ±3 Pin Grid Array PGA Package Leads, P614 Customer Information Fields in the ROM Customer Information Fields in the ROMDevice Production Sequence Speech Development CycleSpeech Development Cycle Device Production Sequence NprfOrdering Information Ordering InformationNew Product Release Forms 614Authorization to Generate MASKS, PROTOTYPES, and Risk Units New Product Release FormsPage Introduction Features Architecture MSP50C605 Preliminary DataArchitecture FeaturesPort Name IO Location MSP50C614 MSP50C605 2 ROM 3 I/O Pins1 RAM Port Description Function Name AddressFigure A±1. MSP50C605 Architecture Data ROM Program MemoryData Memory Peripheral PortsPlastic Package Description Pin# Page Introduction Features Architecture Packaging MSP50C604 Preliminary DataIntroduction Architecture MSP50C604 Preliminary DataFigure B±1. MSP50C604 Block Diagram Host Write Sequence Slave Mode OperationHost Read Sequence Data Memory Program MemoryPeripheral Ports Interrupts Packaging PackagingPlastic Package Packaging MSP50C605 Data Sheet TopicMSP50C605 Data Sheet