Texas Instruments manual ±5. MSP50P614/MSP50C614 Addressing Modes Summary

Models: MSP50C614

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Instruction Syntax and Addressing Modes

Table 4±5. MSP50P614/MSP50C614 Addressing Modes Summary

ADDRESSING

SYNTAX

OPERATION

Direct

name [dest,] [src,] *dma16 [*2] [, next A]

Second word operand (dma16) used directly as memory

 

name *dma16 [*2] [,src] [, next A]

address.

 

 

 

Long Relative

name [dest] [,src] ,*Rx+offset16 [, next A]

Selects one of 8 address registers as base value and adds

 

name *Rx+offset16 [,src] [, next A]

the value in the second word operand. Does not modify the

 

 

base address register.

 

 

Relative to R5 name [dest] [,src] ,*Rx+R5 [, next A]

Selects one of 8 address registers as base value and adds

(INDEX)

name *Rx+R5 [,src] [, next A]

the value in R5. Does not modify the base address register.

 

 

 

Indirect

name [dest] [, src] ,*Rx++R5 [, next A]

Selects one of 8 address registers to be used as the ad-

 

name [dest] [, src] ,*Rx [, next A]

dress, post modifications of increment, decrement, and +

 

name [dest] [, src] ,*Rx++ [, next A]

INDEX(R5) are possible.

 

name [dest] [, src] ,*RxÐ [, next A]

 

 

name *Rx++R5 [, src] [, next A]

 

 

name *Rx [, src] [, next A]

 

 

name *Rx++ [, src] [, next A]

 

 

name *Rx±± [, src] [, next A]

 

 

 

 

Short Relative name [dest] [, src] ,*R6+offset7 [, next A] name *R6+offset7 [, src] [, next A]

Selects PAGE(R6) register as the base address and adds a 7 bit positive address offset from operand field (b6±b0). This permits the relative addressing of 128 bytes or 64 words. Does not modify the PAGE address register. k is shown as constant.

Global Flag

name TFn, dma6

For use with flag instructions only. Adds lower 7 bits of

 

name dma6, TFn

instruction to a fixed address base reference of zero. 64

 

 

fixed flags are addressed by this mode beginning at ad-

 

 

dress 0000h.

 

 

 

Relative Flag

name TFn, *R6+offset6

For use with flag instructions only. Adds lower 7 bits of

 

name *R6+offset6, TFn

instruction(lsb set to zero) to a address base reference

 

 

stored in the PAGE register (R6). 64 flags relative to PAGE

 

 

may be addressed with this mode.

Table 4±6. Auto Increment and Auto Decrement Modes

Operation

Syntax

 

next A

 

 

 

 

 

No modification

 

0

 

0

 

 

 

 

 

Aufto increment

++A

0

 

1

 

 

 

 

 

Auto decrement

±±A

1

 

0

 

 

 

 

 

String mode

 

1

 

1

 

 

 

 

 

Table 4±6 describes the accumulator pointer auto preincrement or predecrement syntax. Not all instructions can premodify accumulator pointers. The next A field is a two bit field using bits 10 and 11 of only certain classes of instructions. Instructions with a [next A] have either a ±±A or a ++A in the instruction. See Table 4±6.

Assembly Language Instructions

4-11

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Texas Instruments manual ±5. MSP50P614/MSP50C614 Addressing Modes Summary, ±6. Auto Increment and Auto Decrement Modes