Texas Instruments MSP50C614 manual ±3. Programmable Bits Needed to Control Reduced Power Modes

Reduced Power Modes

Table 2±3. Programmable Bits Needed to Control Reduced Power Modes

		→ deeper sleep …	relatively less power →
Control Bit	Label for	LIGHT	MID	DEEP
	Control Bit
Idle state clock control
bit 10	A	0	1	1
ClkSpdCtrl register (0x3D)
Enable reference oscillator
bit 09 : CRO or	B	1	1	0
bit 08 : RTO
ClkSpdCtrl register (0x3D)
ARM
bit 14	C	0	1	1
IntGenCtrl register (0x38)
Enable PDM pulsing
bit 02	D	Should be cleared before any IDLE instruction.
DAC Control register (0x34)
IDLE instruction	E	Same instruction is used to engage any of the modes.
(executes the mode)
PLL multiplier		Programmed value is 0 …
bits 07 through 00	F			255 .
ClkSpdCtrl register (0x3D)

MSP50C614 Architecture 2-37